1. What are the differences between the Spartan-II family and Spartan-XL
family?
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The Spartan-II family is:
- Based on a cost-optimized Virtex architecture, while the Spartan-XL
family is based on the XC4000 architecture
- Based on a 0.18u/0.22u, six layer metal (6LM) process vs. a 0.25u/0.35u,
five layer metal (5LM) process for the Spartan-XL family
- 5x density increase (from 40,000 to 200,000 system gates)
- >1.5x speed grade performance (from 100MHz to 150+MHz)
- 2-3x gates per I/O pin
- 2x gates per dollar
- 2x I/O performance
- Operating voltage of 2.5V vs. 3.3V for the Spartan-XL family
- Features dedicated Block SelectRAM in addition to distributed SelectRAM,
while the Spartan-XL family only has distributed SelectRAM memory
- Features dedicated DLLs for advanced clock control, while the Spartan-XL
family does not
- Available in fine pitch packages (FG256 and FG456)
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2. Are the Spartan-II devices bitstream compatible with the Virtex devices?
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Although the Spartan-II devices are based on the Virtex architecture, Xilinx does not guarantee that the Spartan-II devices will be 100% bitstream compatible with Virtex devices.
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3. What are the devices in the family?
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| Device | XC2S15 | XC2S30 |
XC2S50 | XC2S100 | XC2S150 | XC2S200 | | Logic Cells | 432 | 972 | 1728 | 2700 | 3888 | 5292 | | Block RAM Bits | 16,384 | 24,576 | 32,768 | 40,960 | 49,152 | 57,344 | | Max. User I/Os | 82 | 128 | 176 | 196 | 260 | 284 | | Packages | VQ100 | VQ100 | - | - | - | - | | CS144 | CS144 | - | - | - | - | | TQ144 | TQ144 | TQ144 | TQ144 | - | - | | - | PQ208 | PQ208 | PQ208 | PQ208 | PQ208 | | - | - | FG256 | FG256 | FG256 | FG256 | | - | - | - | FG456 | FG456 | FG456 |
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4. How can the Spartan-II DLL be used to multiply the frequency of a clock signal by a factor of four?
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This can be accomplished by feeding the CLK2X output of one DLL into the CLKIN input of a second DLL. The LOCKED signal is fed through an addressable shift register (SRL16) to the RST input of the second DLL. This last connection is ensures that the second DLL will be able to
recognize the change of frequencies when its CLKIN input changes from a 1x waveform to a 2x waveform.
For more information (including a schematic), see XAPP174 and Sparty's Favorite Recipes.
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5. Do the Xilinx FFT Cores support the Spartan-II architecture?
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The Xilinx FFT Cores in the CORE Generator program do not support the Spartan-II family because the FFT cores require more resources than available in the Spartan-II Family. Use the Virtex Family for these cores.
See Answers Database.
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6. Is the new Spartan-II family footprint
compatible with the Virtex family devices?
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No, the Spartan-II family has different features and different package offerings from that of the Virtex family.
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7. How can place and route results be improved without adding timing constraints?
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To improve runtime for timing driven implementation, the place and route defaults have changed to NOT run Cost Based and Delay Based Clean-up passes. Because of this change, you may notice lower design performance results from PAR. This will occur on designs that are run in v2.1i with no timing constraints applied (non-timing driven). To get a more "realistic" estimate of how your design will perform without any timing constraints applied, please follow this recommendation:
- Implement your design until PAR has completed.
- Open up the Flow Engine on your (Routed,OK) revision.
- Under Setup-> FPGA Re-entrant Route, specify the number of clean-up passes to be run.
- Click OK.
- In the Flow Engine, select Flow->Step Back.
- Select Flow->Run.
- Check the Reports Browser (P&R Report/Post Layout Timing Report) for improved performance results.
See Answers Database.
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8. How do I access software support for the
Spartan-II family?
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Spartan-II Family Software Support
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9. How do I access special IOB components in FPGA Express?
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The Spartan-II architecture has special SelectI/O components that allow users to specify the voltage standards each pin must have. These special IOB components exist in the FPGA Express synthesis library but must be instantiated in your HDL code. The components are IBUF, IBUFG, IOBUF and OBUF, and the names are followed by an underscore and then the voltage standard. For example: IBUF_GTL, IBUFG_PCI66_3, IOBUF_HSTL_IV, OBUF_LVCMOS2. A complete list of components understood by FPGA Express can be found in the \lib\virtex directory under the FPGA Express tree (%XILINX%\synth for Foundation users). FPGA Express will understand these components and will not attempt to place any I/O logic on these ports:
Warning: Existing pad cell '/ver1-Optimized/U1' is connected to the port 'clk' - no pads cells inserted at this port. (FPGA-PADMAP-1)
FPGA Express does not merge flip flops into IOBs for the Spartan-II Family. Therefore, you have two options if you wish to have this done; use the map -pr switch to globally (for inputs, outputs, or both) merge flip-flops into IOBs, or instantiate library primitives (FDCE, FDPE) and attach the IOB=TRUE attribute in your HDL code. See Xilinx Solution 4392 for more information about attribute passing in FPGA Express. FPGA Express 4.0 will add the ability to set these voltage standards from within the Constraints Editor.
See Answers Database.
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10. Will the Spartan-II family have the capability to support Internet Reconfigurable Logic (IRL)?
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Yes, the Spartan-II family will incorporate the configuration features of the Virtex Series (including partial reconfiguration) that support our Xilinx On-Line campaign and the concept of Internet Reconfigurable Logic.
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11. Can the Spartan-II devices be configured
through the JTAG port?
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The JTAG Programmer in the 2.1i Xilinx development software supports Spartan-II devices with the installation of Service Pack 6.
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12. What literature is available on the Spartan-II Series?
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Product Overview
Data Sheet 
Application Notes and Xcell Articles
Xilinx at Work in High-Volume Applications
 High-Volume Package Solutions Guide
Core Solutions
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13. What are LogiCORE solutions?
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LogiCORE products are sold, licensed and supported by Xilinx. They are developed internally by Xilinx or jointly with a partner. The cores that Xilinx provides as LogiCORE products typically fall into one of two categories. The first are high-performance interface cores that require a
thorough understanding and control of the FPGA technology and implementation software in order to achieve the desired performance and complexity. An example of a core in this category is the LogiCORE PCI interface. The second category are cores that benefit from a very specialized implementation in the FPGA. An example is the LogiCORE DSP modules that are implemented using a unique algorithm, Distributed Arithmetic. This algorithm fits the lookup-table-based architecture of the FPGA. The result is outstanding performance and device utilization, often more than 10 times better than generic HDL descriptions.
More information
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14. Can the Mode pins be driven High after Boundary Scan configuration?
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A Spartan-II device's mode pins, selected to be inputs after boundary scan configuration, cannot be driven High.
Pre-Configuration
If the mode pins have selected PULLUPs during configuration and the EXTEST or SAMPLE/PRELOAD instruction is loaded the PULLUPs stay active.
If the mode pins have selected FLOATING during configuration and the EXTEST or SAMPLE/PRELOAD instruction is loaded a PULLDOWN is attached to the pin.
Post-Configuration
Regardless of the mode pin selection when the EXTEST or SAMPLE/PRELOAD instruction is loaded the pins keep the same PULLUP/PULLDOWN/KEEPER resistor.
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15. Why does running a design with either BSCAN_SPARTAN2, CAPTURE_SPARTAN2 or
STARTUP_SPARTAN2 generate an "unexpanded" error in ngdbuild?
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The symbols BSCAN_SPARTAN2, CAPTURE_SPARTAN2 and
STARTUP_SPARTAN2 require 3.1i or 2.1i with Service Pack 6.
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16. What are the available packages?
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| Package | XC2S15 | XC2S30 | XC2S50 | XC2S100 | XC2S150
| XC2S200
| | VQ100 |
X | X
| - |
- |
- | -
| | CS144 |
X | X |
- |
- | - |
- | | TQ144 | X
| X |
X | X |
- | -
| | PQ208 |
- |
X | X |
X | X
| X |
| FG256 |
- | - |
X | X
| X |
X | | FG456 | -
| - |
- | X |
X | X
|
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17. What process technology is the Spartan-II family designed in?
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The Spartan-II family is designed in an 0.18u/0.22u, 6LM advanced process technology providing cost optimization and higher performance while remaining 5V tolerant. The Spartan-II family combines 0.22u transistors to maintain 5V compatibility, with 0.18u interconnect to reduce overall die size and provide higher speed.
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18. What are the differences between Spartan-II engineering samples and the production product, regarding JTAG?
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JTAG ID Code
The JTAG ID codes for the XC2S50, XC2S100, XC2S150, and XC2S200 engineering samples are the same as that for the XCV50, XCV100, XCV150, and XCV200, respectively. The final Spartan-II product also has the same "family" designation as the Virtex family;
however, a different "version" designation will give Spartan-II devices a unique JTAG ID code.
JTAG ID Code for Spartan-II Engineering Samples
| Device |
Version |
Family |
Array Row # |
Xilinx Code |
| XC2S50 |
0001 |
0000011 |
000010000 |
0000 1001 0011 |
| XC2S100 |
0010 |
0000011 |
000010100 |
0000 1001 0011 |
| XC2S150 |
0001 |
0000011 |
000011000 |
0000 1001 0011 |
| XC2S200 |
0010 |
0000011 |
000011100 |
0000 1001 0011 |
JTAG ID Code for Production Spartan-II Devices
| Device |
Version |
Family |
Array Row # |
Xilinx Code |
| XC2S50 |
1000 |
0000011 |
000010000 |
0000 1001 0011 |
| XC2S100 |
1000 |
0000011 |
000010100 |
0000 1001 0011 |
| XC2S150 |
1001 |
0000011 |
000011000 |
0000 1001 0011 |
| XC2S200 |
TBD |
0000011 |
000011100 |
0000 1001 0011 |
For more information, see the Spartan-IIdata sheet. Also see the Solution Records on Virtex and Generic IDCODE format.
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19. What are the architectural differences between the Spartan-II, Spartan-XL and Spartan families of FPGAs?
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The Spartan™-II family is based on the Virtex family architecture, while the Spartan and Spartan-XL families are based on the XC4000 Series architecture. The 2.5V Spartan-II devices are a cost-optimized Virtex architecture combining 0.22u transistors for 5V compatibility with 0.18u interconnect. The 5V Spartan devices combine 0.5u transistors, required for the 5V supply, with 0.35u interconnect. Meanwhile, the 3.3V Spartan-XL devices have 0.35u transistors, with a special I/O design for 100% 5V I/O compatibility, and 0.25u interconnect. While the Spartan and Spartan-XL families are footprint compatible with common packages within the series, the Spartan-II family is not footprint compatible with the prior Spartan Series members.
The Spartan-XL family adds the following features to the Spartan family:
- Power down input
- Higher performance to 100 MHz
- Faster carry logic
- More flexible high-speed clock network
- Latch capability in Configurable Logic Blocks
- 12 mA or 24 mA output drive
- Enhanced Boundary Scan
- Express Mode configuration
- Chip scale packaging
The Spartan-II family adds the following additional features:
- Higher performance to 200 MHz
- Higher density to 200,000 gates
- SelectRAM+ hierarchical memory with Block RAM
- Four dedicated DLLs for advanced clock control
- 16 high-performance interface standards
- Dedicated multiplier support
- Cascade chain for wide input functions
- Slave Parallel configuration
- Fine pitch ball grid array packaging
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20. Is the speed naming convention the same for the Spartan-II family as it is for the Spartan and Spartan-XL family?
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Yes, the higher the number, the faster the device is. For example, the XC2S150-6 is faster than the XC2S150-5.
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21. What temperature grades will be available for the Spartan-II family?
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The entire Spartan-II family will be available in the commercial temperature grade (0-85). The industrial range (-40 to 100) will be offered for the -5 speed grade.
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22. Can the Spartan-XL Device Run at Below 3.0V and/or Above 100°C?
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The Spartan-XL family is tested and guaranteed between 3.0V and 3.6V VCC. Industrial devices are tested and guaranteed at up to 100°C junction temperature. Characterization beyond those limits has been
performed and we have found that the devices continue to operate as specified to below 2.7V and above 125°C. Xilinx is confident that all
Spartan-XL devices will continue to meet functionality and I/O level
requirements to 2.7V and 125°C, with VOH and VOL within their specifications relative to VCC. Input thresholds, pull-up resistors, and the
configuration clock stay within their specifications. However, the device will be up to 40% slower at these extended operating conditions. All zero hold times remain at zero. All timing results should be multiplied by 1.4 to generate the expected worst-case value over this extended operating range. These values are not tested or guaranteed.
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23. How Can I Request Literature from Xilinx?
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Xilinx literature can be requested using the on-line form or by contacting your local Xilinx sales office. Information on the new Spartan-II Family is available on-line from the Spartan-II FPGA page. Most other Xilinx literature is also available on-line:
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24. What are AllianceCORE solutions?
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The AllianceCORE program is a cooperative effort between Xilinx and independent third-party core developers. It is designed to produce a broad selection of industry-standard solutions dedicated for use in Xilinx programmable logic. Xilinx takes an active role with its partners in the process of productizing AllianceCORE products. This is unique to the AllianceCORE program. Because the process is so involved, we work closely with our partners to select the right cores first which helps raise the quality and usability of the cores that are offered.
More information
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25. What are the differences between the Spartan-II family and the Virtex family since the two are based on the same architectures?
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Spartan-II FPGAs are a cost-optimized Virtex architecture designed in an 0.18u/0.22u, six-layer-metal process, while Virtex FPGAs use different process technology. From a price standpoint, the Spartan-II family features more aggressive pricing than the Virtex family. Spartan-II FPGAs do not have the two temperature diode pins found on Virtex FPGAs. The Spartan-II family is available in only the most popular and lowest cost package parts, which results in lower prices to our customers, and will share only two common packages with the Virtex family, which are the FG256 and FG456 fine-pitch ball grid array packages.
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26. Are Spartan-II FPGAs pin-to-pin compatible to prior Spartan Series product offerings?
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No, the Spartan-II FPGA is based on a cost-optimized Virtex architecture and is neither pin-to-pin nor software compatible with prior
Spartan Series product offerings, which are based on the XC4000 architecture.
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27. What routing advantages does the Virtex architecture provide for the Spartan-II family?
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The much richer routing resources and the basic Virtex architecture will result in very fast compile times (on the order of 100,000 gates per minute) for the Spartan-II family with high performance results as well. This will enable the Spartan-II family to produce very predictable results in a short time for HDL users.
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28. What operating voltage will the Spartan-II family perform to?
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The Spartan-II family will run at 2.5V operating voltage and is designed for 3.3V and 5V I/O compatibility.
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29. What is the Spartan-II Family?
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The Spartan-II family is the next generation family of the Spartan Series based on the industry-leading Virtex architecture. The Spartan-II family extends the portion of the ASIC market that Xilinx can address, while leveraging off the features and performance of the Virtex architecture. The Spartan-II family is a 0.18u/0.22u, 2.5V family offering six devices in densities up to 200,000 system gates.
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30. What software supports the Spartan-II family?
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The latest software release, version 3.1i of Xilinx Alliance Series and Foundation Series software, offers full support for the Spartan-II family. The Spartan-II family software support is available in version 2.1i via a key upgrade (except for the XC2S200). Xilinx and other EDA vendors, including Exemplar, Synopsys and Synplicity offer support via VHDL and Verilog synthesis.
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31. What are the available IP cores for the Spartan-II family?
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More than 66 cores are available for use in the Spartan-II family. This includes parameter-driven, Smart-IP-based LogiCORE modules and the Real-PCI solutions from Xilinx as well as cores from third-party developers in the Xilinx AllianceCORE program.
Xilinx offers more than 34 DSP and general-purpose LogiCORE modules. These include memory compilers, asynchronous dual-port FIFOs, high-performance multipliers, and FIR filters.
The Real-PCI solution for Spartan-II devices includes Internet-accessible 32-bit and 64-bit PCI LogiCORE modules, synthesizable PCI bridge reference designs with basic DMA and Block RAM based FIFOs. A power management reference design is also available, along with other reference designs provided as HDL source code.
More than 32 cores that are sold and supported by AllianceCORE partners are available for use in Spartan-II FPGAs. They cover applications ranging from wireless communications, networking and video to embedded computing. Functions include SDRAM controllers, Reed Solomon and Viterbi decoders, 10/100 Ethernet media access controllers, UTOPIA interfaces and video color space converters.
For links to all core solutions for the Spartan-II Family, go to the IP Center.
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