Re: Clarifying the Verilog and SV compatibility issue.

Hi Shabtay,

> From a use model perspective, SV models/BFMs will have to be compiled in
> SV mode using a SV compiler directive (switch) while "old Verilog" will
> have to be compiled using the Verilog compiler, unless the Verilog code
> is searched for existence of new SV keywords and modified.

One thing to keep in mind is that SCE-MI requires the infrastructure
linker to be run on the HDL code.  The infrastructure linker would
somehow know (the user probably tells it) what language the HDL is
written in.  The infrastructure linker finds the exported/imported
functions calls and replaces it with something the backend of the
toolset can understand.  Even if the bulk of the HDL code is to
be considered old Verilog, you could still use the SystemVerilog DPI
syntax for the function calls as the infrastructure linker will
take care of them.  However, if the code uses new SystemVerilog
keywords you would obviously not be able to run this code in a
SystemVerilog simulator unchanged.  In other words, SCE-MI 2.0
models written in old Verilog will still need a third party
SCE-MI 2.0 implementation to run on simulators regardless of
whether we choose to support the attribute-based function calls
or the DPI syntax (the latter being equivalent to not supporting
old Verilog, more or less).

Per

-- 
Per Bojsen                                Email: <bojsen@zaiqtech.com>
Zaiq Technologies, Inc.                   WWW:   http://www.zaiqtech.com
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