Subject: Fwd: Stu Sutherland's take on PLI/VPI/DirectC (from ESNUG Post 38)
From: Joao Geada (Joao.Geada@synopsys.com)
Date: Fri Aug 02 2002 - 06:47:54 PDT
( ESNUG 398 Item 11 ) -------------------------------------------- [07/31/02]
From: Stuart Sutherland <stuart@sutherland-hdl.com>
Subject: These Fruity Flavors Of C Doesn't Mean Verilog's PLI Is Going Away
Hi John,
In past ESNUG newsletters, and in other forums, there has been a lot of
discussion about how Synopsys DirectC and/or Co-Design's Cblend and/or
SystemVerilog will replace the Verilog PLI. As a true-blue PLI bigot (I
wrote that big 850 page book on using the PLI) and one who makes a living
doing Verilog PLI training and consulting, I keep getting questions about
how much longer will the Verilog PLI be around, and will my business die
when there is no PLI. So, if you will permit me to use your ESNUG forum, I
would like to set the record straight on the difference between Synopsys's
DirectC and the Verilog PLI.
For the majority of us that use Verilog, the Verilog PLI currently serves
two major roles. In its first role, the PLI allows third-party software
tool vendors or in-house CAD departments to write applications that are
portable -- perhaps with a tweak or two--to all major Verilog simulators.
The Verilog PLI serves as a uniform layer between the application and the
simulator's internal data structures. In addition, the PLI's interface
layer allows those software tools to analyze a simulator's data structure
and search for specific information, without the application needing to
know anything at all about how the simulator has organized its data
structures. Without a standard procedural interface, every application
would have to be rewritten for each and every simulator.
In its second role, the PLI allows those of us who do design and/or
verification to access the C language from within Verilog source code.
This is a great feature, and in my bigoted opinion, it is one of the
reasons for Verilog having been so successful. However, even as a PLI
bigot, I must also candidly admit that I think the PLI is very ill-suited
for this second usage. The PLI is cumbersome and difficult to learn.
Design and verification engineers have to jump through too many hoops
just to access C code from their Verilog code. More importantly,
because the PLI's is an interface layer, it is inherently inefficient for
run-time performance. Using the PLI to mingle C code with Verilog code is
an abuse of what the PLI was designed for. In essence, when designers use
the Verilog PLI just to call a C function, they are using a 20 pound sledge
hammer to do the job of a 4 ounce tack hammer.
DirectC and Cblend satisfy the need of the second type of PLI user. They
allow a mingling of C code with Verilog code, without the need of the
complex Verilog PLI. However, DirectC and Cblend are proprietary to their
respective companies, which limits the usage to only those companys'
software products. Accellera's SystemVerilog 3.0 standard, ratified in
June 2002, adds some C capabilities to Verilog as a true, nonproprietary
standard. Both Synopsys and Co-design have donated--or are planning to
donate--the work they have done with DirectC and Cblend to Accellera, so
that they can be standardized as part of SystemVerilog. All three
approaches solve the PLI abuse problem. Design and verification engineers
can hook their Verilog and C code together directly in the Verilog
language, without having to learn and use an industrial strength procedural
interface.
However, DirectC, Cblend and SystemVerilog do not replace what the PLI can
do very well, which is provide a universal interface to any compliant
simulator. Software tools that need to access the internal data structures
of a simulator, and have the program work with any simulator, need a true
interface layer. There is, and I think there always will be, a need for
the Verilog PLI.
I applaud the work that Synopsys and Co-design have done to give design and
verification engineers the capabilities they need without having to use the
PLI. I also applaud them for opening up that work to Accellera so that it
can be standardized as part of SystemVerilog. And I'm not at all worried
about this integrated C capability taking away my business of Verilog PLI
training -- I have a SystemVerilog training course, too. ;)
- Stu Sutherland
Sutherland HDL, Inc. Tualatin, OR
==============================================================================
Joao Geada, PhD Sr. Staff R&D Engineer Verif Tech Group
Synopsys, Inc TEL: (508) 263-8083
154 Crane Meadow Road, Suite 300, FAX: (508) 263-8069
Marlboro, MA 01752, USA
==============================================================================
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