Subject: RE: Confirmed List of Attendees and Interesting Statistics -- 23 Attendees
From: Vassilios.Gerousis@Infineon.Com
Date: Tue Sep 03 2002 - 21:00:45 PDT
No room in th inn. Sorry. The meeting is closed for others.
> -----Original Message-----
> From: Gerousis Vassilios (CL DAT CS)
> Sent: Tuesday, September 03, 2002 12:21 PM
> To: Gerousis Vassilios (CL DAT CS); 'sv-ac@eda.org'; 'sv-bc@eda.org';
> 'sv-cc@eda.org'; 'sv-ec@eda.org'
> Cc: 'Jayant Nagda (E-mail)'; 'Grant Martin (E-mail)'
> Subject: RE: Confirmed List of Attendees and Interesting Statistics
> -- 23 Attendees
>
>
>
> Latest Count 25 out of 25 limit
>
> -----Original Message-----
> From: Gerousis Vassilios (CL DAT CS)
> Sent: Monday, September 02, 2002 12:58 PM
> To: 'sv-ac@eda.org'; 'sv-bc@eda.org'; 'sv-cc@eda.org';
> 'sv-ec@eda.org'
> Cc: Jayant Nagda (E-mail); Grant Martin (E-mail)
> Subject: Confirmed List of Attendees and Interesting
> Statistics
>
> Confirmation of List of Attendees:
>
> A- Statistics:
> a- Number of EDA vendors: 16 attendees.
> b- Number of Users: 10 attendees.
> c- Active IEEE 1364 members: Mac could you please
> check the list.
> d- Accellera members: 13 attendees.
>
> B- The List --- 25 out of 25 (cut-off number).
>
> 1- Ambar Sarkar
> ambar.sarkar@paradigm-works.com
> Principal Consulting Engineer Phone: 978-824-1363
> Paradigm Works Cell: 508-561-1868
>
> 2- KC Chen [kchen@verplex.com]
> Verplex Systems, Inc.
>
> 3- Erich Marschner, Cadence Design Systems
> Senior Architect, Advanced Verification
> Phone: +1 410 750 6995 Email: erichm@cadence.com
>
> 4- David W. Smith - Synopsys -- Chairman of SystemVerilog
> Enhancement Committee
> Synopsys Scientist
>
> 5- Dennis Brophy, Model Technology / Mentor Graphics -
> Accellera Chairman
>
> 6- Richard C. Ho (rho@0-in.com) Tel:
> 408-487-3647
>
> 7- Kevin Cameron [dkc@grfx.com] National Semiconductor
>
> 8- Bassam Tabbara [bassam@novas.com]
>
> 9- Simon Davidmann [simond@co-design.com]
>
> 10- Yatin Trivedi - Consultant -- Chairman of C Interface
> Committee.
>
> 11- Karen Pieper [Karen.Pieper@synopsys.com]
>
> 12- David Fong [dfong@s3graphics.com] S3 Graphics
> Design Verification Manager
>
> 13- Grant Martin - [gmartin@cadence.com]
> Fellow, Cadence Labs tel. +1-510-647-2804
>
> 14- Faisal Haque - Cisco, fhaque@cisco.com - Chairman of
> SystemVerilog Assertion Committee.
>
> 15- Siamak Arya [siamak@telairity.com] Telairity
> Semiconductor, Inc.
>
> 16- Jayant Nagda - Synopsys.
>
> 17- Stephen Meier - Synopsys.
>
> 18- Vassilios Gerousis - Infineon Technologies. - Chairman
> of SystemVerilog Committeen and TCC chairman.
>
> 19- Rajeev K. Ranjan Rajeev Ranjan
> [rajeev@realintent.com]
> Director, R&D
> Real Intent
>
> 20- Kurt Takara [ktakara@0-In.com]
>
> 21- Alec Stanculescu [alec@fintronic.com]
>
> 22- Stuart Sutherland.
> 23- David Kelf Dave Kelf [davek@co-design.com]
24- Stefenen Boyd Stefen Boyd
[stefen@boyd.com]
25- Mehdi Mohtashemi mehdi@synopsys.com
> Best Regards
>
> Vassilios
>
>
> --------------------------------------------------------------------------
> ----------------------------------------------------
> Dr. Vassilios Gerousis
> Chief Scientist
> Infineon Technologies
> DAT CS, MchB
> D-81541 Munich
> Germany
> BalanSt. 73
> Telephone: +49-89-234-21342
> Fax: +49-89-234-23650
> email: Vassilios.Gerousis@infineon.com
> Site Map:
> http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
>
> --------------------------------------------------------------------------
> --------------------------------------------------------
>
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