Subject: Joao Geada
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Alain,
my reply follows each of your questions below.
alain@tensilica.com said:
As donated, it is an API and a C preprocessor. The C preprocessor
> 2) I liked some concepts such as the idea that Verilog modules could be
It covers functions and modules, and yes, no renaming is necessary. The
NOTE: "hard" requirement => has to be addressed, as opposed to a "soft"
Technically, the issues are very similar:
Thank you,
Joao
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To: Alain Raynaud <alain@tensilica.com>
Cc: sv-cc@server.eda.org, Joao Geada <Joao.Geada@synopsys.com>
Subject: Re: Comments on DirectC
In-reply-to: Your message of "Thu, 26 Sep 2002 10:42:18 PDT."
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Date: Thu, 26 Sep 2002 14:07:10 -0400
From: Joao Geada <joao@jurassic.synopsys.com>
> 1) is DirectC a language or an API (or both)? I didn't quite understand
> the mechanism by which the preprocessor extracts C code from a Verilog
> file.
takes some Verilog'ish text (always, initial, @(expr)) and substitutes some
appropriate C text.
"always" & "initial" blocks become function definitions,
"@(expr)" statements become function calls
> replaced by C modules transparently. This looks a lot like the FLI in
> VHDL and it's a good thing. Is this extended to functions and tasks?
> Ideally, the caller should not have to know whether it is calling
> Verilog or DirectC: the function name should not change, for instance
> (and adding "$" in front of a name is a change).
only thing that changes to replace a Verilog definition with a C definition
is to change the definition, and similarly to change a C definition with
a Verilog definition only the definition itself changes.
This was one of the "hard" requirements for directC, that the usage of
a function/module not change regardless of whether it is implemented
as a Verilog function/module or a directC function/module.
requirement.
> 3) Regarding calling Verilog tasks from DirectC, is there any technical
> reason why it can't be done (syntax, scheduling...)? Otherwise, I assume
> we could add it at some point, since there is so much demand for it. And
> it fits the idea above that C and Verilog modules and tasks could be
> swapped transparently.
in both cases you need a thread running the C code. This thread is suspended
when waiting for simulation time or simulation events.
- With DirectC you suspend on the functions that wait for simulation time
and that wait for signals to change, and resume when the event occurs.
- To invoke a Verilog task, you suspend on its invocation, resume when the
task completes.
> 4) I agree with the comment that DirectC should not reinvent the whole
> PLI, especially the callback mechanisms.
============================================================================
==
Joao Geada, PhD Sr. Staff R&D Engineer Verif Tech
Group
Synopsys, Inc TEL: (508)
263-8083
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263-8069
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==