Subject: Vote on the assertion API
From: Francoise Martinolle (fm@cadence.com)
Date: Mon Oct 07 2002 - 15:23:50 PDT
I am voting NO on behalf of Cadence because I cannot accept a technical
proposal for
an assertion API *before* the assertion language or System Verilog
extensions for assertions are defined.
Secondly I believe that the assertion API should be defined as VPI
extensions if the assertions are part of the language otherwise we would
have 2 APIs ( VPI and SV-AssertionAPI)
to access the same thing. You should be able to traverse your design using VPI
and use also VPI to access the assertions and not switch to a different API.
note: that the API that is proposed has the same access mechanisms as VPI
(iterators, callbacks, ...) which reinforces my opinion regarding the
feasibility of
extending VPI to access assertions.
Lastly, the assertion API as presented and defined is insufficient in terms
of the access that would be needed by 3rd party tools. We should have more
detailed requirements for the
assertion API.
Francoise
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