Subject: ISSUE:DirectC:DirectC i/f should support mechanism for calling Verilog task/function from a DirectC application
From: Swapnajit Mittra (mittra@juno.com)
Date: Sat Oct 19 2002 - 20:52:23 PDT
ISSUE:DirectC:DirectC i/f should support mechanism
for calling Verilog task/function from a DirectC
application
I believe this has been discussed many times over email
and in the meetings. I am formally filing this as an ISSUE
to keep a record of this. (The other emails related to this
proposal are attached below).
As many of you had pointed out earlier, the idea of calling
a Verilog task or function from a C function is not new,
and has been there in CBlend/Superlog for some time. I am
proposing the following at the risk of being redundant if
a CBlend donation takes place in the future.
In any case, here are my proposals.
o A DirectC application shall be allowed to call a Verilog
task or function from a C function similar to a call to
another C function.
o If an external C function calls a Verilog task, no
simulation time must elapse during the execution of that task.
(This is, because a C function in DirectC is a zero-time event).
However, no such restriction shall be in place when a Verilog
task is called from a cmodule.
o The type of the arguments and the return type (for a Verilog
function) shall be one of the types allowed by DirectC for
a Verilog task or function calling a C function.
o The called Verilog task or function can be specified from
the DirectC domain by Verilog full pathname. (This will
allow us to call a specific Verilog task or function in
the design hierarchy. We need to think about the actual
syntax of this).
==================================================================
Previous emails on this subject:
On Sep 24 2002, Swapnajit Mittra wrote:
...
o It appears to me (and somebody pointed this out during
the meeting too) that in DirectC there is no straightforward
way of calling a Verilog task from C function. I mention this
because I run a Verilog PLI related website and I get the
question on how to call a Verilog task from C function
(reverse direction of PLI) regularly. I believe CBlend of
Superlog provides this already. I think we should consider
providing this feature in SV-CC too.
...
On Sep 26 2002, Stuart Sutherland wrote:
...
I agree that there should be a mechanism for C functions to call
Verilog tasks.
...
On Sep 26 2002, Alain Raynaud wrote:
...
3) Regarding calling Verilog tasks from DirectC, is there any technical
reason why it can't be done (syntax, scheduling...)? Otherwise, I assume
we could add it at some point, since there is so much demand for it. And
it fits the idea above that C and Verilog modules and tasks could be
swapped transparently.
...
On Sep 24 2002, Joao Geada wrote:
Swapnajit,
you are correct, DirectC includes no functionality for
invoking Verilog tasks from within the C code, though
it does posses mechanisms to wait on Verilog signals
and to wait for a specific amount of time to pass. As
many people seem interested in this other direction (C
invoking Verilog), it seems reasonable that this be
added to the DFLI requirements. Once it is in the
requirements, we, as a committee, can work on extending
the donations to support this capability.
...
On Oct 07 2002, Doug Warmke wrote:
...
*** C-calls-HDL task/function feature ***
DirectC lacks a C-calls-HDL task/function feature.
We should add that feature with similar syntax.
i.e. the function call looks like C, but in fact
is implemented in SV. The linker/elaborator would
bind the runtime image based on function name,
just like a C linker. The CBlend binding mechanism
allowed for that. Would there be any problem from
the Synopsys/Co-Design point of view if that aspect
of CBlend was resurrected in the SV standard?
...
(Please send me a pointer to any other email on this
that I may have missed. I will add them to the list.)
- Swapnajit.
-- Swapnajit Mittra http://www.angelfire.com/ca/verilog
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