Subject: RE: ISSUE:DirectC:DirectC i/f should support mechanism for callin g Verilog task/function from a DirectC application
From: Warmke, Doug (doug_warmke@mentorg.com)
Date: Mon Oct 21 2002 - 17:30:56 PDT
Swapnajit,
Some brief comments on your proposal.
We can discuss more at the appropriate time in the meeting or in email.
>
> o If an external C function calls a Verilog task, no
> simulation time must elapse during the execution of that task.
> (This is, because a C function in DirectC is a zero-time event).
> However, no such restriction shall be in place when a Verilog
> task is called from a cmodule.
>
I think this is overly restrictive. It will not work out well if
some implementations want to directly integrate C models
living in a threaded environment (e.g. TestBuilder, SystemC)
together with HDL models. Let's keep an open mind
about making large scale changes to DirectC.
>
> o The called Verilog task or function can be specified from
> the DirectC domain by Verilog full pathname. (This will
> allow us to call a specific Verilog task or function in
> the design hierarchy. We need to think about the actual
> syntax of this).
>
This is a good requirement. We need to be able to specify
specific instances of tasks or functions on the other side
of the language boundary. The same applies for C functions
called by the HDL side.
Thanks for the movement on technical discussion of
DirectC issues, Swapnajit.
Regards,
Doug Warmke
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