Subject: Re: DirectC: external modules vs. external/exported tasks
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Wed Nov 06 2002 - 17:17:49 PST
> From owner-sv-cc@server.eda.org Wed Nov 6 17:05:43 2002
> From: "Andrzej Litwiniuk" <Andrzej.Litwiniuk@synopsys.com>
> Subject: DirectC: external modules vs. external/exported tasks
> To: sv-cc@server.eda.org
>
> Fellow committee members,
>
>
> VCS DirectC (Synopsys donation accepted by this committee)
> provides only one mechanism for synchronizing Verilog and non-Verilog
> components: the external modules.
> IMO both sides of the external modules should be seen and considered
> separately. The proposed C++ based realization of external modules,
> i.e. cmodules, is just one of possible forms of a 'plug-in' for an external
> module. The particular syntax, which combines Verilog-like constructs
> with C++ code is not critical here. Possibly it can be replaced by plain
> C++ code and some library.
> What is the essence of this mechanism is the paradigm that synchronization
> is based on module port events and that Verilog and non-Verilog components
> communicate, synchronize and exchange data via ports.
> Personally I feel that this is elegant a mechanism and fully in a spirit
> of HDL. (I mean the Verilog side of external module interface. Wheteher
> cmodule is palatable, is another story.)
>
> Question: is alternative mechanism needed?
>
> There have been strong demands to add the capability to call a task
> from either of two languages, SV and a foreign language.
> Specifically, to be able to call SV tasks from C.
>
> IMO such mechanism is fully orthogonal to external modules.
> It will provide alternative means for synchronization.
>
> It's easy to observe that if C may call SV task and SV may call C task
> (i.e. a function that may block/wait/pass time), then the whole synchronization
> can be expressed in SV.
> Simple SV tasks may be defined in with wait, delay, etc.
> Such tasks can be then used on C side as synchronization primitives.
> So, C function would delay or wait by calling primitive SV task which contains
> the needed delay or wait.
>
> Resuming: external modules and external/exported tasks are two indepenedent
> and orthogonal mechanisms for synchronization.
>
> Are both these mechanisms needed or we will give up one of them and pursue
> only the other one?
>
> Thanks,
> Andrzej
I'd say that between SV (with the enhancements tabled in the EC committee) and
SystemC, "cmodule" is redundant functionality. If you can cross-call the callee
probably shouldn't worry about who the caller is.
Kev.
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