Subject: Re: Modified Proposal ... - modified syntax for "export"
From: Stickley, John (john_stickley@mentorg.com)
Date: Wed Nov 20 2002 - 08:58:37 PST
Andrzej,
I like the idea of making the cname optional as you suggest.
However I kind of like the flow of the english sentence better with
"as".
export [modulename::] function fname [as cname];
Kind of rolls off the tongue easier don't you think ?
But either way is fine with me.
-- johnS
Andrzej Litwiniuk wrote:
Basically I've added an "as clause" to the basic export declaration
to declare globally scoped C alias to a locally scoped Verilog task:
export_decl ::=
export access_mode ? attribute (, attribute) * ?
function | task [modulename::]fname as cname;
access_mode ::= ( "A" | "C" )
attribute ::= pure | context
John,
Although this is a minor issue, I propose to modify the syntax for
the export declaration.
Note that the whole information about the exported function or task is
available to SV compiler, so there is no need to provide redundant
information like function/task; also attribute, access_mode seem
irrelevant
here. Also a new keyword "as" better be avoided.
I recon that the gist of your proposal is cname. The syntax may look as
follows:
export_decl ::= export [cname] [modulename::] fname ;
cname is optional here, it will default to fname (for example, for
functions
defined in $root scope).
Andrzej
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