Subject: External model proposal #2
From: Warmke, Doug (doug_warmke@mentorg.com)
Date: Mon Dec 02 2002 - 09:25:55 PST
Hi Everyone,
Here is the external model proposal, reworded as per
our agreements at the meeting on last Tuesday.
extern module (<port list>);
<parameter declarations> // If ANSI-C style ports and params are not
used
<port declarations> // If ANSI-C style ports are not used
<all other module items>
endmodule
The only new point is the addition of the "extern"
keyword in front of any normal SV module definition.
Notes:
a) At SV elaboration time, no declarative or body items of
external models are elaborated. It is assumed that the
foreign implementation will handle the model's elaboration.
b) When binding an external model into an instantiation,
the generics and ports of the model are bound as if the
model were not external. i.e. All normal type, size,
and direction requirements for ports and parameters are
applicable.
c) It is possible for users to include declarative items
and statement parts (body) in external models.
As mentioned in a), these are ignored by the SV elaborator.
However, such items must be composed of legal SV syntax.
d) It is possible for SV simulators to include binding
information in an optional attribute item in the module.
For example, a shared object name and entry point function
might be appropriate in some cases.
Hopefully the LRM writers can gracefully condense this
information into the existing SV LRM draft. If any of you
others have other fine points that need to be highlighted,
please add them to this mail thread.
****************
Background:
General requirements for this feature are:
1) Syntax consistency with SV external tasks/functions
2) Consistency with established VHDL syntax and semantics
The syntax for SV external function declarations is effectively:
extern <attributes> <function name> <parameters> ;
Refresher on VHDL external model syntax:
entity <Ename> <generics and ports> end;
architecture <Aname> of <Ename> is
attribute foreign of <Aname> : architecture is
"<implementation-specific information>";
begin
end;
Some interesting semantic points of VHDL external models:
a) At elaboration time, no declarative or body items of
foreign design units are elaborated. This applies to both
the foreign architecture and its associated entity.
b) When binding an external model into an instantiation,
the generics and ports of the model are bound as if the
model were not external. i.e. all type, size, and
direction requirements still apply.
c) It is possible for users to include declarative items
and statement parts (body) in foreign models. As mentioned
in a), these are ignored by the VHDL elaborator. As far as
I know, however, such items must be legal VHDL and must
pass through the VHDL analyzer.
d) It is common for VHDL simulators to include binding
information in the <implementation-specific information> field.
Shared object names and entry point functions are common.
Thanks and regards,
Doug Warmke
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