Subject: RE: [sv-cc] Another directC C mapping question
From: Francoise Martinolle (fm@cadence.com)
Date: Mon Feb 03 2003 - 05:17:26 PST
In the case of a negative integer on the Verilog side, it would be declared
as a signed int but when it is passed to C it is transformed into
an unsigned int, therefore the value seen by the C code would be unsigned.
If the C code needs to know it needs to be interpreted as a signed value
how it would know if we transform any signed value to an unsigned value on
the C side?
For example, if in Verilog I declare a variable c:
signed char c = -1;
extern myCfunc(c); //C function which takes c as a parameter
On the C side the parameter c is seen as unsigned char I believe.
void myCfunc(unsigned char c)
{
int i;
i = c;
printf("c = %d\n", i); //This will print 255 instead of -1
}
This is a general issue of how do we pass the signedness to the C side?
Francoise
'
At 03:30 PM 1/30/2003 -0800, Bassam Tabbara wrote:
>I don't understand the question. The bits would be in 2's complement ...
>
>-Bassam.
>
>--
>Dr. Bassam Tabbara
>Technical Manager, R&D
>Novas Software, Inc.
>
>http://www.novas.com
>(408) 467-7893
>
> > -----Original Message-----
> > From: owner-sv-cc@server.eda.org
> > [mailto:owner-sv-cc@server.eda.org] On Behalf Of Francoise Martinolle
> > Sent: Thursday, January 30, 2003 3:12 PM
> > To: sv-cc@server.eda.org
> > Subject: [sv-cc] Another directC C mapping question
> >
> >
> > Andrzej,
> > another few questions...
> >
> > 1 st question:
> >
> > If we consider a 4 bits register:
> > reg [4:1] r;
> > to pass to a directC function, given what is proposed
> > it would be represented in C as a unsigned int where only the
> > first 4 bits
> > would be
> > significant. I am assuming that the remaining bits would have
> > to be filled
> > with 0s.
> > MSB is bit 4 and LSB is bit1. In verilog 2001 LRM, MSB if
> > left bound of the
> > range and
> > LSB is right bound of the range.
> >
> > Let say that the value of r is: b'0110
> >
> > The C code would retrieve the value as an unsigned int, the
> > value would be 6.
> >
> > What about if we have a signed register:
> >
> > signed reg [4:1] r;
> > How would the C code knows that the value is signed? In case
> > the verilog
> > value is negative,
> > the C value must be seen as negative.
> >
> > Thanks
> >
> > Francoise
> > '
> >
> >
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