Subject: Re: [sv-cc] DirectC C Layer - encoding of x/z
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue Feb 04 2003 - 16:30:09 PST
> From Andrzej.Litwiniuk@synopsys.com Tue Feb 4 16:05:43 2003
>
> > > /* canonical representation */
> > >
> > > #define sv_0 0
> > > #define sv_1 1
> > > #define sv_z 2 /* representation of 4-st scalar z */
> > > #define sv_x 3 /* representation of 4-st scalar x */
>
> KEVIN:
> > Value, strength and certainty are orthogonal, this would be better as:
> >
> > #define sv_0 0
> > #define sv_1 1
> > #define sv_z 2 /* representation of 4-st scalar z */
> > #define sv_x 4 /* representation of 4-st scalar x */
> >
> > - this is relevent if you are bridging into a mixed-signal/analog environment.
>
> The proposed representation of x and z is consistent with Verilog 1364-1995
> standard, see LRM p. 340:
>
> aval bval value
> ---------------------
> 0 0 0
> 1 0 1
> 0 1 z
> 1 1 x
Yes, but like I said: value, strength and certainty are orthogonal. VCS and I'll
assume some other simulators collapse the 6 values to 4 as an optimization.
Collapsing the values causes problems with mixed signal simulation where you
need the 1s and 0s to close simulation loops.
Kev.
> I assumed that numerical representation is calculated as {bval,aval}.
>
> BTW, I prefer VCS notation with "c" and "d" fields, cf. svLogicVec32,
> because it seems more intuitive: "c" stands for "control" and "d" stands for
> "data".
>
> Andrzej
>
>
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