Subject: Re: [sv-cc] another directC question - skipping params? No way!
From: Andrzej Litwiniuk (Andrzej.Litwiniuk@synopsys.com)
Date: Tue Feb 11 2003 - 15:13:58 PST
I took for granted that arguments to external functions (DirectC) called
from SV code are passed solely on position base and must not be skipped.
We wanted same rules and same syntax for calling functions or tasks
regardless whether they are external or native SV functions or tasks.
I don't think that arguments to SV functions or tasks may be either skipped or
passed by name. Unless something has changed and I missed it, Verilog used to
permit such tricks (arguments by names or skipped) only for module instantiating.
Please correct me if I'm wrong.
Andrzej
> Francoise,
>
> do you mean "We should not allow to skip to provide a parameter if a default value is NOT provided" or
> do you want to forbid skipping parameters at all? This is not clear to me ...
>
> -Michael
>
>
> Francoise Martinolle wrote:
> > I am digging more in the directC document and I found something which needs
> > to be specified:
> > directC functions which are called from within Verilog must have all the
> > parameters specified on the call either by position or by name. We should
> > not allow to skip to provide a parameter if a default value is provided in the function
> > declaration for that argument.
> >
> > Francoise
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