Subject: RE: [sv-cc] more about import/export
From: Joao Geada (Joao.Geada@synopsys.com)
Date: Fri Mar 07 2003 - 15:19:09 PST
I think a number of people are making a mistake confusing the context of a function vs the location where
a function is called. In Verilog, functions run in the context where they are defined *not* where they are
called from.
Specifically, the only variables a function can "see" without qualification are the variables that occur in its
context, not those visible in the location where it was called.
For example:
module foo(input clk);
reg a, b; // top level decls
function dummy(input bar);
a = bar;
endfunction
always @(posedge clk) begin
...
dummy(b); // call 1
...
begin: myblock
reg a; // local decls
...
dummy(b); // call 2
end
...
end
endmodule
(plz forgive any syntax erros). In the above example, both call 1 and call 2 cause the same variable, the top-level
a, to be modified, even though in call2's local scope there is a different version of "a" available.
In short: for a SV function, context is always where the function was declared, not where it was called from.
I hope this explanation clarifies the definition of "function context": it is the context where the
function was declared (ie where the extern appears, or where the function definition of an exported function appears)
and is conceptually, just the fully qualified name of that function (minus the function name part itself).
Joao
==============================================================================
Joao Geada, PhD Principal Engineer Verif Tech Group
Synopsys, Inc TEL: (508) 263-8083
344 Simarano Drive, Suite 300, FAX: (508) 263-8069
Marlboro, MA 01752, USA
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