Subject: Re: [sv-cc] Updated LRM
From: Francoise Martinolle (fm@cadence.com)
Date: Tue Mar 18 2003 - 06:31:18 PST
At 08:54 PM 3/17/2003 +0000, Simon Davidmann wrote:
>I have a couple of comments/questions.
>
>1) section 3.3. FSM
>I do not see the purpose of this section for several reasons
>- it does not adhere to V2K attributes, but to tool styles which are
>surely to be deprecated - in V2K you should be using attributes not
>commented pragmas
>- SystemVerilog3.0 has enums so why even discuss old style illegal
>parameter style pragmas..
>
>and the more I look the more I think we need to kill this section
>completely as it has nothing to do with SystemVerilog, but is all about
>the old style of usage of Verilog95.
>
>2) I notice lots of references to the Synopsys donation technology DirectC
>in the document - are we using this name? I thought not, maybe I am out of
>sync... Surely this is a Synopsys product name and should not be used by
>Accellera. In fact it always used to Accellera policy to change the names
>of things - as it is not the donation but a new Accellera owned technology.
>
>3) also I note references to SystemVerilog 'byte' type - which I thought
>had now be removed, as char is always 8 bit.
In fact the contrary was decided at yesterday's BC meeting:
issue BC-86: the deletion of char in SV was approved and byte remains.
>Simon
>
>
>At 07:17 PM 3/17/2003, Joao Geada wrote:
>>Hi all,
>>
>>attached is an updated sv-cc draft LRM. The following changes are in:
>>- update to assertion API (as per Bassam & Surrendra's update from sv-ac)
>>- update to the DirectC C-layer section (includes context funcs + all of
>> Andrzej's et all corrections and enhancements)
>>
>>Note that the extern/export syntax has *NOT* been put into the revision
>>(as the final accept only happened Thursday there was not time to fold it
>>into
>>the lrm).
>>
>>Jo
>
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