Subject: RE: [sv-cc] more assertion issues
From: Joao Geada (Joao.Geada@synopsys.com)
Date: Thu Apr 17 2003 - 08:55:49 PDT
Francoise,
These issues were already addressed while addressing the sv-cc LRM issues
(this was issue LRM-34)
Note that all sv-cc LRM issues have been addressed; We should now be focusing on ensuring
that all the LRM sections are consistent with each other and identifying any errors
(if any) that may have been missed by the other reviewers.
Joao
==============================================================================
Joao Geada, PhD Principal Engineer Verif Tech Group
Synopsys, Inc TEL: (508) 263-8083
377 Simarano Drive, Suite 300, FAX: (508) 263-8069
Marlboro, MA 01752, USA
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-----Original Message-----
From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org]On Behalf Of
Francoise Martinolle
Sent: Thursday, April 17, 2003 10:38 AM
To: joao.geada@synopsys.COM
Cc: sv-cc@eda.org
Subject: [sv-cc] more assertion issues
the entire bullet 6) should be removed?
6) Any assertion updates from the SV-AC.
The following 2 should be realigned:
— Assertion source information: the file, line, and column where the assertion is defined.
— Assertion clocking domain/expression
I believe that we should change assertion clocking domain/expression
to assertion resolved clock expression because the chapter 17 talks
about clock resolution for an assertion.
Francoise
'
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