RE: [sv-cc] Mail from ["Clifford E. Cummings" <cliffc@sunburst-de sign.com>]


Subject: RE: [sv-cc] Mail from ["Clifford E. Cummings" ]
From: Warmke, Doug (doug_warmke@mentorg.com)
Date: Tue Aug 05 2003 - 16:03:18 PDT


Hi Cliff,

MTI has committed to donating technology that will
allow C to call SV tasks that consume time.

Note that not just any C code will be able to do so.
Only context import functions will be able to call
exported tasks. This is the same as the current rules
for calling exported functions.

And not just any code will be able to call such context
import functions: Only call chains originating in
SV procedural code will be allowed to perform such
interlanguage calls from C to SV.

What this means is that some arbitrary PLI code,
say an end-of-compile callback or a VCL callback,
will not be able to call a SV task. I don't think
Superlog allows such call chains (I refer to them
as "out-of-the-blue" calls into SV) either. Please
let me know if that is a wrong thought.

Any other preliminary comments would be appreciated as well.

Regards,
Doug Warmke
Director R&D, MTI South

-----Original Message-----
From: Swapnajit Mittra
To: sv-cc@eda.org
Sent: 8/5/2003 3:35 PM
Subject: [sv-cc] Mail from ["Clifford E. Cummings"
<cliffc@sunburst-design.com>]

   FYI.

--
Swapnajit Mittra
Project VeriPage ::: http://www.angelfire.com/ca/verilog

---------- Forwarded Message ----------

Date: Tue, 05 Aug 2003 11:06:25 -0700 To: sv-cc@server.eda.org From: "Clifford E. Cummings" <cliffc@sunburst-design.com> Subject: Request: Call time-consuming Verilog tasks from C

Hello SV-CC Committee -

I tried to do a search on this topic from the sv-cc email repository and it looks like the subject was somewhat addressed last October, but I am not sure.

Superlog had the ability to call Verilog tasks from C - a rather nice feature that is not currently in SystemVerilog.

I could have a posclk task that waited for a posedge clk, and call it from C. Now I could have multiple clocks and still schedule C-events with respect to the different clocks. This was already implemented in a vendor tool (a key requirement for new SV 3.1a proposals), and this capability meant I did not have to use SystemC to consume time in a simulation. I could use plain old C.

This was a key selling point for Superlog. I was quite disappointed to find that SystemVerilog could not do this. As a user, I would like to see this capability donated from Synopsys (Co-Design-Superlog) and added to SystemVerilog.

Regards - Cliff Cummings ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, Synthesis and Verification Training

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