Subject: Re: [sv-cc] SystemVerilog 3.1A Meeting on September 18th
From: Swapnajit Mittra (mittra@juno.com)
Date: Tue Sep 09 2003 - 07:56:55 PDT
For the three donations related to SV-CC, I would
like to request the donors (Synopsys for SVPI,
Mentor for task related donation and Novas for
VCD) to send a copy of the donation related slides
to the email reflector (sv-cc@eda.org). This
will let the people on the phone to sync up with
the presentation.
-- Swapnajit Mittra Project VeriPage ::: http://www.angelfire.com/ca/verilog-- Vassilios.Gerousis@Infineon.Com wrote: Dear SystemVerilog Committee Members, Our first 3.1A face to face meeting is now confirmed for September 18. Synopsys has agreed to host our meeting. The meeting will occur in Hopper Conf Rm on the 1st floor of Synopsys Sunnyvale Bldg 2 which is on Mary near Maude in Sunnyvale. Those who registered will have a badge waiting for them. I will send direction and a map as soon as I get it. For those people who registered, and do not plan to attend this meeting, please send me a cancellation notice so that someone else can take your place. We will have a teleconference available for those who wish to join us by phone. Here is the phone information: U.S. dial-in # > 888-635-9997 Intl dial-in # > 763-315-6815 Participant code > 742766# Please do not expect to hear everything on the phone. We will make sure that each presenter can speak near a telephone speaker. We will not send slides in advance. Do not ask for the slides. Please let me know if you want to join by phone, so than we can make sure that the line will be open.
SystemVerilog 3.1A - Agenda
9:00 - 9:15 - Introduction. 9:15 - 10:15 SV Committee Status 15 minutes - SystemVerilog Design Committee - Johny/Karen. 15 minutes - SystemVerilog Assertions - Faisal / Arif 15 minutes - SystemVerilog C/API - Swapnajit / Ghassan 15 minutes - SystemVerilog Testbench - David / Neil.
10:15- 10:30 Break.
10:30 ---- Donations/Proposals. 30 Minutes - Synopsys Proposals. 30 Minutes - Novas VCD extension Proposals. 30 Minutes - Mentor Proposals (Separate Compile and C/API). 30 Minutes - Bluespec - Behavioral Synthesis Donations.
12:30 - 1:15 Lunch / Discussions.
1:15- 2:00 - 3.1A Milestones and Activities. - Synchronization between SV committees. - Feedback, Action Items and Adjournment of SV Meetings.
2:00 - 2:15 Break and preparation for next meeting: People signed for this are Synopsys, Mentor, Apteqs, Axis, and Novas. Anyone else must tell me in advance if they plan to attend this session. Those who plan to attend should provide a slide for what they would like to see.
2:15 - 5:00 PM Accelerated Testbench Kick Off Meeting. (This was originally a proposal By Motorola to examine how to accelerate SystemVerilog Testbench and Assertions.) - Introduction of the kick-off. - The need for such a committee: Opinions. a- Axis. b- Apteqs. c- Mentor. d- Synopsys. - Why it is not a Synthesizable Testbench? - Proposals a- API. b- ? - Summary of Results and Recommendation to continue this effort or not.
SystemVerilog 3.1 Standard Is Available Now . SystemVerilog Enjoys More than 40 EDA vendors products planned for end of this year and 1Q of 2004. It is the fastest growing EDA support for a young standard with innovative new technologies. Stay tuned to www.systemverilog.org <www.systemverilog.org> for latest announcements.
Best Regards
Vassilios Gerousis
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