Subject: [sv-cc] CC meeting minutes
From: Francoise Martinolle (fm@cadence.com)
Date: Wed Nov 12 2003 - 14:09:27 PST
Last meeting minutes
*************************
Joao propose acceptance of the minutes, Doug seconded. Passed
Review of issues:
**********************
bc77 nothing to do with the CC commitee
behaviour of disabling of tasks/functions
Keep it the same as Verilog: undefined: Assignment values to task function
arguments cannot not be assumed be made after a disable occurs (not true
for assignments to refs and globals ).
VPI presentation:
**********************
We reviewed diagram after diagram
variables:
---------------
integer var is missing
Iteration on Bits from the variable class does not make sense.
Should probably be bitvar ->> bit
See notes 9 and 2 => Joao needs to resolve and provide explanation.
Bitselect/;partselct issue: cannot bitselect an integer, real variable but
can you bit select another typed variable such as a packed variable?
The variable diagram tried to merge the reg diagram and variable diagram
redundant info for variable driver and load iterations (should have the
same names tags)
classvar should have 2 properties indicating associative array or dynamic array
note: cbSizeChange.
Joao also considered to have cbtypechange (only for classes) as classes are
dynamic anc be assigned to other classe instances
Michael: needs to define the order in which sizeChange and valueChange
change callbacks would occur.
1364 drivers and load were only for single bits
in SV they apply to the whole variable and certain part selects of the variable
The notes for driver/load needs to be more complete and detailed. Probably
an example would be very helpful
unpacked array variable: you can assign a sub-array
drivers at the variable level should include array, array slice, element array
Joao thinks that drivers and lads for reg and variables are not very
useful, more useful would be readers and writers (should be an enhancement
for Verilog 1995 for reg and vars)
scope class:
------------------
arrow back to scope is missing
note needed about names of unnamed begin and forks: random name will be
generated by each simulator
packages: a package would be a sub-class of instances
also need to add import clause and take care of $unit
property isImported for each declaration
clocking domains are missing from scope
iodecl:
----------
new: iteration on ranges? pass multiple dimensional array on io port as
argument on ports.
module should be instances (module, interface, program) can have iodecls now
Joao says that adding representation of types in VPI would break backward
compatibility because types were represented flat in Veriglo2001? Francoise
does not understand this concern. VPI access to types are useful for
decompilation purpose and type compatibility checks.
scope:
----------
an assertion is not static so it is not a scope
automatic variables are not returned from a scope
a class contains static data is a scope
classdefn to be able to represent definitions.
clocking domain
-------------------------
should have a fullname property
Replace name and direction relationships with properties.
\ input foo = expr, foo is the name, direction is input
input a, b, c, d => 5 decls instead of iterating on vpiExpr
should have vpiisdefault property to not that the skew is default
change vpiSkew relationship to expr to be a relatoinship to an unnnamed
class containing an edge control or delay control
For example of dege control skew see 3.1Adraft 1: page 138
class definitions:
-----------------------
classes can exist when they are static classes without anyone instantiating
them.
extern and virtual? sv does not have virtual? Joao to check
Dpi extern and export. properties and context need to be added as well as a
property to to get the exported C name
waiting process should return a frame or a process?
Frame:
-----------
frame: missing arrow back to a statement
frames have been changed from 1364 allow to have frames to exist for scopes
2 reasons: scopes containing fork join are frames, scopes can contain
automatic variables, processes blocked waiting.
alias statement
------------------------
error: 1 to 1 relation needs to be replaced by an iteration from an
instance to alias stmts
alias only of nets? Joao to check
Threads:
------------
a thread is a stack of frames
fork join creates threads
in SV many active frames.
fork join
In Verilog 1364 frames are always for task and functions which are reentrant.
because automatic variables can be in static task makes the reason for
having frame even for static tasks and functions
Assertions:
-----------------
assertions: concurrent and procedural assertions
broad overview given on the assertion part.
PropertySpec:
missing arrow back from variables to propertySpec
Propertyexpr:
should instead be an operation with a vpiOptype property which can return
vpiimplyOp, vpidelayedImplyOp,...
SequenceExpr:
Francoise: why is an expr a sub-class and you can iterate on assignments
from it?
Disabling on task and functions:
----------------------------------------------
added 2 functions one to check the disable state of a function call chain
and one to acknowledge that it has recognized that the call chain was
disabled. This allows the proposal to work for functions.
items 6 and 7 were also added
Voting by next Wednesday on Doug proposal
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