Subject: RE: [sv-cc] SystemVerilog Coverage API (chapter 28) proposed errata
From: Bassam Tabbara (bassam@novas.com)
Date: Tue Nov 18 2003 - 09:21:34 PST
Joao [I cut down the cc-list in case you meant for the errata to be
final ...]
One comment, the "vpiCovered" spec does not sit well with me. Seems like
you say as long at it has been attempted and succeeded at least once.
That is good, but we also need to add that *it never failed*. A fail
seems to invalidate the "covered". Otherwise the "vpiCovered" really has
not much meaning, it is same as "vpiAssertSuccessCovered". WDYT ?
** What do users think about this ? Comments ?
Also just a minor thing too, "vpiAssertSuccess/FailCovered" mean attempt
+ success/fail. This is so obvious it does not even need mention, just
picky I am :-)!
-Bassam.
Joao wrote:
...
> vpi_get(vpiCovered, assertion_handle)
....
> For assertions, vpiCovered implies that the assertion has
> been attempted and succeeded at least once. More detailed
> coverage information can be obtained for assertions by the
> following queries:
>
> vpi_get(vpiAssertAttemptCovered, assertion_handle)
> vpi_get(vpiAssertSuccessCovered, assertion_handle)
> vpi_get(vpiAssertFailureCovered, assertion_handle)
>
> which respectively indicate that the assertion has been
> attempted, succeeded or failed at least once.
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