Subject: RE: [sv-cc] Assertion API questions
From: Bassam Tabbara (bassam@novas.com)
Date: Wed Nov 26 2003 - 08:50:20 PST
John, thx for the review, please see my comments below. All, since this
is a "discussion item" for today's meeting, please skim my comments if
you wish.
-Bassam.
-- Dr. Bassam Tabbara Technical Manager, R&D Novas Software, Inc.http://www.novas.com (408) 467-7893
> -----Original Message----- > From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On > Behalf Of Amouroux, John > Sent: Tuesday, November 25, 2003 11:50 AM > To: 'sv-cc@server.eda.org' > Subject: [sv-cc] Assertion API questions > > > Hi folks (remember me?), > > I've been going through our assertion api section in the SV > 3.1 spec more thoroughly and I have a few questions/comments. > > 1. On page 249, paragraph 27.3.2.1, we have the structure > t_vpi_assertion_info. In there is a field called defname. > It is declared as a PLI_BYTE8 and I think it should be a PLI_BYTE8*.
Yep, I think so too. Need to add to errata.
> 2. On page 251, paragraph 27.4.2, the struct > t_vpi_attempt_info contains a field called attemptTime. > Given a property that takes more than one clock cycle to > complete, does attemptTime represent the time the property > was started or the time at which the property was found to > not hold? Later parts of the doc seem to imply that this is > a start time, but it should be explicitly mentioned here.
Yes, I had filed an errata about this (and addition of a seperate cb_time callback field). > 3. (same place as #2) In the structure t_vpi_attempt_info > there is a field called failExpr. Since it appears that this > same struct will be used for stepping operations, and a > property when in the middle of a step is not necessarily > failing, should it really be called something like currentExpr?
I don't think so, that's a union 2 separate callbacks.
> 4. Last paragraph on page 251, first sentence, if I > understood everything correctly, I would like to add the word > "instance" (or scope?) to the sentence. i.e. "These > callbacks are specific to a given assertion instance;".
Well throught the chapter the wording "assertion" really means an assertion "instance" (aka object). So I would opt that we not make this correction so as not to confuse reader (with *attempt* and so on...). Of course, we can choose to add the word "instance" but must be *all over* the chapter but again I think that's not needed, and may be even confusing.
** May be we can add a word or two to explain this equivalence somewhere in this area (see the "***", the simplest change I can think of :-)!!), WDYT ?
"27.3 Static information This section defines how to obtain assertion handles and other static assertion information. 27.3.1 Obtaining assertion handles SystemVerilog extends the VPI module iterator model (i.e., the instance) to encompass assertions (****i.e. assertion instances*****), as shown in Figure 27-1. The following steps highlight how to obtain the assertion handles for named assertions.
Copyright 2003 Accellera. All rights reserved. 247"
> 5. On pages 252-253, paragraphs 27.5.1-2, we have an apparent > ambiguity in our vpi function naming. More precisely, I > don't see how we can differentiate between the various > vpi_control function calls described here given a standard C linkage.
Johnny, this is not a new issue, vpi_control already has varargs, so this does not add new routines, just new usage (semantic actions if you will), from V2K
"Copyright C 2001 IEEE. All rights reserved. 665 27.3 vpi_control() vpi_control() Synopsis: Pass information from user code to simulator. Syntax: vpi_control(operation, varargs) Type Description Returns: PLI_INT32 1 (true) if successful; 0 (false) on a failure Type Name Description Arguments: PLI_INT32 operation select type of operation varargs variable number of operation specific arguments Related routines:"
> Thanks, > Johnny
Thanks Johnny, here's my summary of (immediate) fixes, will wait for your input and team discussion on the other items I explained above:
ADD to errata filed recently (your "1" and "4"):
"On page 249, paragraph 27.3.2.1, we have the structure t_vpi_assertion_info. In there is a field called defname. It is declared as a PLI_BYTE8 and I think it should be a PLI_BYTE8*."
And MAY BE the following if we all agree this makes sense:
P. 247: "27.3 Static information This section defines how to obtain assertion handles and other static assertion information. 27.3.1 Obtaining assertion handles SystemVerilog extends the VPI module iterator model (i.e., the instance) to encompass assertions (****i.e. assertion instances*****), as shown in Figure 27-1. The following steps highlight how to obtain the assertion handles for named assertions."
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