RE: [sv-cc] Meeting reminder - 02/11


Subject: RE: [sv-cc] Meeting reminder - 02/11
From: David W. Smith (dwsmith@synopsys.com)
Date: Tue Feb 10 2004 - 23:50:47 PST


I have these on the list of items to include in Draft 5. Is there something else that needs done?

Regards
David

-----Original Message-----
From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of Warmke, Doug
Sent: Tuesday, February 10, 2004 11:19 PM
To: 'Swapnajit Mittra'; sv-cc@eda.org
Subject: RE: [sv-cc] Meeting reminder - 02/11

Swapnajit,

Last week I sent a mail to sv-cc detailing several
errata in our DPI sections that need to be fixed.
But no response has come from you or any other member
of SV-CC. In discussing with Joao, we both feel
these errata are important to get fixed in SV 3.1a.
I am reincluding the items here (plus one new
erratum, courtesy of Ralph), so that we can
discuss in conference tomorrow.

1. Scalar return values of type bit and logic.
   These were inadvertently omitted from the list in 27.4.5.

   ADD new bullet item to the list in 27.4.5:
      - scalar values of type bit and logic

2. In Annex E, Section E.6.4, no mention is made of bit and logic.

   ADD two new rows to Table E-1:
      bit unsigned char
      logic unsigned char

   In addition, add a footnote symbol (*) in the "bit" and "logic"
   table cells. The related footnote text should read:

     "Encodings for bit and logic are given in file svdpi.h.
     Refer to Section E.9.1.1."

3. In Annex E, Section E.7.9, no mention is made of bit and logic.

   ADD a new bullet item as follows
      - scalar values of type bit and logic

   ADD a new paragraph just after the bullet list:

      "Encodings for bit and logic are given in file svdpi.h.
       Refer to Section E.9.1.1."

4. There is no clear mention of unsigned SystemVerilog types
   in the LRM. A strict interpretation of the LRM may even
   indicate that we don't support unsigned SystemVerilog types.
   This was certainly not in the spirit of SV-CC's 3.1 work.

   ADD a new paragraph just after table E.1 as follows:

      "The DPI interface also supports the SystemVerilog and C
       unsigned integer data types that correspond to the mappings
       Table E-1 shows for their signed equivalents."

5. Ralph's new erratum on part select indexing direction.

   Crux: Comments for part select functions in svdpi.h
         do not explicitly state the indexing direction
         from the start bit (i.e., whether the 'starting
         bit index' is the part's low bit or high bit).

   ADD the following to both Sections E.10.3.2 and F.1.
   It should be the final line in the existing comment
   block shown below:

   " * Selected part's range in both arrays will be [w+i-1:i]."

   /*
    * functions for part select
    *
    * a narrow (<=32 bits) part select is copied between
    * the implementation representation and a single chunk of
    * canonical representation
    * Normalized ranges and indexing [n-1:0] are used for both arrays:
    * the array in the implementation representation and the canonical
array.
    *
    * s=source, d=destination, i=starting bit index, w=width
    * like for variable part selects; limitations: w <= 32.
    * Selected part's range in both arrays will be [w+i-1:i].
    */

Thanks,
Doug

> -----Original Message-----
> From: owner-sv-cc@server.eda.org
> [mailto:owner-sv-cc@server.eda.org] On Behalf Of Swapnajit Mittra
> Sent: Tuesday, February 10, 2004 8:48 PM
> To: sv-cc@server.eda.org
> Subject: [sv-cc] Meeting reminder - 02/11
>
>
>
>
> We will have a short meeting tomorrow to quickly
> go through the status on Draft 4 review. I have
> only two main items on the agenda:
>
> 0. Procedural works [Swapnajit, 5 minutes]
>
> 1. Any feedback/comment on schedule deadlines
> that I sent earlier. [All, 5 minutes]
>
> 2. Status of the review process:
> Parts A through E. Ralph and Francoise will not
> be present tomorrow and we will postpone discussion
> on those parts.
>
> A: Francoise
> B: Doug
> C: Ralph
> D: Bassam and Michael (for the parts that Bassam requested)
> E: Michael.
> BNF/Header files: Joao (please synch up with BNF editor on
> this).
>
> o Conference info:
> 9-10 AM PST.
>
> To attend the weekly meeting, please call:
> (888) 635-9997 (US toll free) or
> (763) 315-6815 (International)
> And use the passcode: 2638073
> --
> Swapnajit Mittra
> Project VeriPage ::: http://www.angelfire.com/ca/verilog
>
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