Subject: [sv-cc] Fw: Last Call for Papers - EDP 2004 - Design Process Workshop
From: Swapnajit Mittra (mittra@juno.com)
Date: Fri Feb 13 2004 - 18:30:11 PST
Fwding as per Steve Grout's request.
-- Swapnajit Mittra Project VeriPage ::: http://www.angelfire.com/ca/verilog---------- Forwarded Message ----------
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Last Call for Papers
ELECTRONIC DESIGN PROCESSES -- EDP 2004
http://www.eda.org/edps/edp04/
April 25-27, 2004, Monterey Beach Hotel, Monterey, CA
IEEE Computer Society Sponsored by Technical Committee on Design Automation In cooperation with ACM/SIGDA ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
The Electronic Design Processes (EDP) Workshop provides a forum for a cross-section of the design community to discuss state-of-the-art electronic design processes and CAD methodologies. As the requirements and complexities of electronic design increase, past ad hoc approaches to design processes are proving inadequate. The workshop focuses on the facilitation and improvement of the overall design process, rather than on the functions of the individual tools themselves. Topics include interactions among and between tools and designers, the infrastructures supporting these interactions, and the frameworks in which these interactions take place.
FOCUS IN 2004: Methodologies for Energy-Aware High-Performance Systems
We solicit papers and proposals for special/panel sessions that shed light on the methodologies used for real, current and future chip and system designs. Methodology aspects of interest include but are not limited to:
1. Best practices and experiences Domain-specific methodologies: SOC, analog / mixed-signal, RF
2. Metrics Cost, time-to-market, productivity
3. Flow integration/optimization Scaling and migration Scaling to diskbusters Co-evolution of methodology and process technology
4. Human issues Large/distributed design teams Training and education
5. Manufacturing integration Process/device characterization, modeling
6. Domain-specific methodologies Functional verification RTL-down implementation HW/SW co-design IP reuse
7. Key trends Future methodology needs and concepts Impact of design-manufacturing interface Process advances and multi-technology integration New tool/algorithms Interoperability Impact of the web, licensing models, and platforms
All papers must be submitted electronically through the website or by email to jantonio@us.ibm.com. Authors should submit full-length, original and unpublished papers (maximum 20 pages in single-column double spaced format, or 6 pages in double-column conference proceedings format) along with author contact information. Proposals for special and panel sessions may also be submitted; a 1-page description along with organizer contact information is required.
IMPORTANT DATES
Submission deadline February 15, 2004 (Please contact jantonio@us.ibm.com if you need an extension.)
Acceptance notification March 1, 2004 Camera-ready copy due March 31, 2004 On-site registration April 25, 2004
STEERING COMMITTEE
Juan-Antonio Carballo (IBM) Aparna Dey (Cadence) Steve Grout Dwight Hill (Synopsys) Takahide Inoue (STARC) Andrew B. Kahng (UCSD) José Augusto Lima (Univ. of Minho) Stefanus Mantik (UCLA/Cadence) Gabe Moretti (EDN) Naresh Sehgal (Intel) Gary Smith (Gartner/Dataquest)
General Chair: Juan-Antonio Carballo (IBM Research) Technical Program Chair: Dwight Hill (Synopsys) Publicity Chair: Aparna Dey (Cadence)
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