[sv-cc] Mail freom Charles Dawson <chas@cadence.com>

--
Swapnajit Mittra
Project VeriPage ::: http://www.angelfire.com/ca/verilog
Date: Thu, 25 Mar 2004 17:39:12 -0500
From: Charles Dawson <chas@cadence.com>
Reply-To: chas@cadence.com
To: Francoise Martinolle <fm@spaz.boston>, sv-cc@server.eda.org
CC: chas@spaz.boston, joao.Geada@synopsys.com
Subject: Re: Other errata for VPI
Here's a few more:
  - 31.28
      The dotted enclosure reference "constraint" should be a solid
      enclosure.
  - 31.37
      There are references to "break" and "continue".  These do not
      have definitions anywhere, nor are they in the include file.
  - 31.38
      The definition "return stmt" should be "return".
   -Chas
Francoise Martinolle wrote:
> The instance diagram (31.12) shows iteration on scopes, processes, 
> defparam and clocking blocks for packages, this is wrong according to 
> the BNF which does not allow these things to be declared in packages.
> 
>  Additionally, the access to the default clocking should be removed from 
> a package reference handle.
> Array of packages does not make sense so the iteration on instances from 
> an intance array returning a package should be removed, same for 
> accessing the index (vpiIndex) of a package array element.
> 
> Additionally the vpiFullName of a package should be defined. As SV 
> allows to have package names be the same a module names, we have a 
> potentially ambiguity with look up by hierarchical name if both top 
> level modules and packages have the same name.
> If something is declared in $root or in $unit, what is his fullname of a 
> global thing or the fullname of a global thing living to a compilation 
> unit? This is undefined at the moment.
> Can vpi_handle_by_name return handles to things defined in the global 
> name space of a compilation unit?
> Can vpi_handle_by_name found imported items from a scope handle to a 
> module importing the package. I would expect that the answer is no, 
> since the imported item is not declared in the module but is just imported.
> 
> Can we resolve these issues?
> 
> Francoise
>        '
> 
> 
> 
-- 
Charles Dawson
Senior Member of Consulting Staff - Project Lead
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com
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