[sv-cc] VPI issues to be addressed

Hi all,

in addition to Francoise's errata/questions below, there is one other significant
thing for us to address: dealing with references used in expressions. Currently
this is not at all addressed in our VPI models.
The simplest thing seems to have references appear as an additional type of object
in simple expressions.

Other issues:
diagram 31.14 (instance arrays):
  the relation to range (on lhs of the diagram) should be an iterator, rather than
  a 1-to-1 relation. This relation is intended to model multi-dimensional arrays.
  Additionally I believe we also need a property to describe whether an array is
  multi-dimensional or not.

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Francoise's errata list:

Errata #1:
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Section 31.12 Typespec
Note 1 is incorrect:
there is not typeSpec to typespec relationship. There is a vpiTypedefAlias relationship
There is no vpiTypedefType property. There is instead a vpiTypedef property.
I believe that the correct wording should be"

If the vpiTypedef is TRUE, then the vpiTypedefAlias shall return a non null handle which represents a handle to the aliased typedef.
Ex:
typedef enum bit [0:2] {red, yellow, blue} primary_colors;
typdef primary_colors colors;

If "h1" is a handle to the typespec colors, its vpiType shall return a vpiEnumTypespec,
the vpiTypedef property shall be true, the vpiName property shall return "colors", the vpiTypedefAlias shall return a handle "h2" to the typespec "colors" of vpiType vpiEnumTypespec.
The vpiTypedef property shall be false for h2 and its vpiTypedefAlias shall return null.

Errata #2:
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We need to have another note specifying that a type is defined as an alias of another type, it inherits the vpiType of this other type.
Ex:
typedef time my_time;

my_time t;

The vpiTypespec of the variable named "t" shall return a handle h1 to the typespec "my_time" which vpiType shall be a vpiTimeTypespec.
The vpiTypedefAlias applied to handle h1 shall return a typespec handle h2 to the predefined type "time".

Question:
I am wondering if we shouldn't add a property vpiPredef to determine if a typespec is a predefined type: real, time, realtime, integer, logic, bit... are all predefined Verilog or systemVerilog types. This would allow to differentiate from user define aliases of predefined types without having to get their names.

Francoise
       '

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Joao Geada, PhD Principal Engineer Verif Tech Group
Synopsys, Inc TEL: (508) 263-8083
377 Simarano Drive, Suite 300, FAX: (508) 263-8069
Marlboro, MA 01752, USA
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Received on Wed Apr 14 08:50:19 2004