[sv-cc] Errata for SV3.1A (Multiple Packed Array Dimensions)

Below is a problem that Doug found; we might want to add it to the DB
and address it via P1800.

Please let me know if you have counter-suggestions for the solution.

Thanks for considering this one,

Ralph Duncan
-------------

1. Contradictory treatment of multiple packed dimensions (Sections
E.6.6, E.10.1)

Section E.6.6 requires that multiple packed array dimensions be
linearized,
which implies they are an acceptable construct:

        "1) If a packed part of an array has more than one dimension, it
is
        linearized as specified by the equivalence of packed types (see
Section 4.2)."

However, section E.10.1 states "Packed arrays shall be one-dimensional,"

which implies that the construct is illegal.

There are two problems:
. Cross-reference to Section 4.2 does not address packed type
equivalence (5.8.1 does).
. The E.10.1 statement contradicts the E.6.6 statement.

Suggestion-1: Correct cross-reference in E.6.6:

Before: "(see Section 4.2)."

After: "(see Section 5.8.1)."

Suggestion-2: Reword E.10.1

Before: "Packed arrays shall be one-dimensional. Unpacked arrays can
have an
        arbitrary number of dimensions."

After: Multiple packed dimensions of a System Verilog array are
linearized.
        Unpacked arrays can have an arbitrary number of dimensions."
Received on Tue Aug 10 10:35:06 2004