Looking forward, I think a common instance of connecting C to SystemVerilog will be a SystemC model. Unlike C, SystemC has a concept of sized busses, registers, etc. as well as timing constructs.
The SystemVerilog standard, as it now stands, does not really address the special issues that a SystemC interface would entail. For example, the ability to directly and easily connect busses and scheduling issues between the two.
This seems like issues which need to be addressed in the DPI / VPI and appropriate to discuss in this committee.
Rob Slater
Freescale Semiconductor (FSL)
r.slater@freescale.com
Received on Wed Nov 3 05:52:38 2004
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