RE: [sv-cc] Proposal uploaded for #72, #288

I would prefer svUint32_t. We should keep "Bit" out
of the name so that readers don't specialize it to
SystemVerilog "bit" variables as opposed to "logic"
variables. And "sv" followed by one upper case letter
is consistent with how Appendix E declares other
types.

Regards,
Jim Vellenga

---------------------------------------------------------
James H. Vellenga 978-262-6381
Engineering Director (FAX) 978-262-6636
Cadence Design Systems, Inc. vellenga@cadence.com
270 Billerica Rd
Chelmsford, MA 01824-4179
"We all work with partial information."
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] -----Original Message-----
] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On
] Behalf Of Michael Rohleder
] Sent: Wednesday, November 10, 2004 3:43 AM
] To: Warmke, Doug
] Cc: Michael Rohleder; SystemVerilog CC DWG
] Subject: Re: [sv-cc] Proposal uploaded for #72, #288
]
] Hello Doug,
]
] I have chosen the name sv32BitUnsignedInt_t due to my lack of
] creativity, lazyness, and not willing to spend more time on
] finding better/shorter names ;-) . I am happy to use any
] better name you or anybody else come up ... 8-)
] W.r.t. other names: I would only define those, when this is
] needed -- to my understanding, we are currently only require
] the usage of 32 bit integers. Keep in mind, the idea is not
] to define them, but require to use them to be always correct
] with respect to integer sizes.
]
] Regards,
] -Michael
]
] Warmke, Doug wrote:
]
] Michael,
]
] In #288, the name chosen is sv32BitUnsignedInt_t.
] That is a lot of typing. Could we use svuint32_t
] svUint32_t, or sv_uint32_t instead?
]
] Also, do we want to define other size and signedness
] variations of int, now or in the future?
] svuint64_t, svint32_t, for example?
] I guess if those types would never be used in the
] standard header files, they are not strictly necessary.
] But perhaps a programming nicety for DPI users.
]
] Regards,
] Doug
]
]
]
] -----Original Message-----
] From: owner-sv-cc@eda.org
] [mailto:owner-sv-cc@eda.org] On
] Behalf Of Michael Rohleder
] Sent: Tuesday, November 09, 2004 9:16 AM
] To: SystemVerilog CC DWG
] Subject: [sv-cc] Proposal uploaded for #72, #288
]
] As said in the subject.
]
] Regards,
] -Michael
]
] --
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Received on Wed Nov 10 08:08:21 2004