[sv-cc] CC related changes to the proposal for data types on nets.

The datatype group reviewed the proposal for data type on nets but they
want the CC committee to review the few LRM changes that are related to data
type on
nets which were found in the sections of the sv31a LRM for which the CC
committee
is responsible.
I would like to have these changes discussed at the next CC meeting.
Feel free to reply to this message before the meeting.
 
The proposed changes are:
 
----------------------------------------------------------------------------
-

SECTION E.9.2 Source-level compatibility include file svdpi_src.h

CHANGE:

Only two symbols are defined: the macros that allow declaring variables to
represent the SystemVerilog packed arrays of type bit or logic.

TO:

Only two symbols are defined: the macros that allow declaring C variables to

^ represent SystemVerilog data objects that are packed arrays of bit or
logic.

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

----------------------------------------------------------------------------
-

ANNEX F: section F.2

CHANGE:

/* macros for declaring variables to represent the SystemVerilog */

/* packed arrays of type bit or logic */

/* WIDTH= number of bits,NAME = name of a declared field/variable */

TO:

/* macros for declaring C variables to represent SystemVerilog data objects
*/

/* that are packed arrays of bit or logic */

/* WIDTH= number of bits,NAME = name of a declared field/data object */

----------------------------------------------------------------------------
-

IN ANNEX I:

CHANGE:

#define cbTypeChange 605 /* callback on variable type/size change */

TO:

#define cbTypeChange 605 /* callback on object data type/size change */

^^^^
Received on Wed Nov 17 13:25:18 2004