RE: [sv-cc] Item 313: PTF 296: Generate stmts will need change made in VPI

From: Jim Vellenga <vellenga@cadence.com>
Date: Mon Nov 22 2004 - 12:13:57 PST

Charles,

I believe the proposal needs to make a clearer distinction
between the "gen var" and the corresponding implicitly
defined local parameters. The "gen var"

-- belongs to the the parent scope of the generate, and
as such has a vpiFullName that does not include the
name of the "gen scope"

-- carries no value once the design has been elaborated.

Each local parameter, on the other hand,

-- belongs to one of the generated "gen scopes"

-- has the same vpiName as the "gen var"

-- has a vpiFullName that includes the name of the
"gen scope" that it belongs to.

-- has a value in the elaborated design corresponding
to the value that the "gen var" had when the "gen scope"
was elaborated.

Also, I believe generates can be nested, so that it
should be possible for a "gen scope array" to be
embedded in a "gen scope".

Also, I believe (but am not sure) that a "gen scope"
for a generate-conditional or generate-case would
be embedded directly within a parent "module" or
"gen scope", rather than in an "gen scope array".

I apologize ahead of time if I've missed some earlier
resolution, since I'm relatively new to the PTF.

Regards,
Jim Vellenga

---------------------------------------------------------
James H. Vellenga 978-262-6381
Engineering Director (FAX) 978-262-6636
Cadence Design Systems, Inc. vellenga@cadence.com
270 Billerica Rd
Chelmsford, MA 01824-4179
"We all work with partial information."
----------------------------------------------------------
  
 

] -----Original Message-----
] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On
] Behalf Of Charlie Dawson
] Sent: Thursday, November 18, 2004 5:13 PM
] To: SV-CC
] Subject: [sv-cc] Item 313: PTF 296: Generate stmts will need
] change made in VPI
]
] I have posted a proposal for enhancing VPI to support generates.
] Please find attached to Item 313.
]
] Thanks.
]
] -Chas
]
]
] --
] Charles Dawson
] Senior Engineering Manager
] NC-Verilog Team
] Cadence Design Systems, Inc.
] 270 Billerica Road
] Chelmsford, MA 01824
] (978) 262 - 6273
] chas@cadence.com
]
]
]
]
Received on Mon Nov 22 12:14:03 2004

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