Re: [sv-cc] Errata #63, #158, #330 amended as discussed in today's meeting

I did here the best of what was possible with M$-Word.
No I don't want to give any guidance on formatting, I know people can
discuss about this for ages.

Stu should pick on formatting scheme he likes and keep this throughout
the document ...

Regards,
-Michael

Jim Vellenga wrote:

>Looks good, Michael.
>
>I do have a question about the formatting of the coding
>in F.1 in both 205 and 330. The spacing, indentation,
>etc., seems a little irregular, though technically correct.
>Do we want to give Stu some specific guidance on the
>formatting?
>
>Regards,
>Jim V.
>
>---------------------------------------------------------
>James H. Vellenga 978-262-6381
>Engineering Director (FAX) 978-262-6636
>Cadence Design Systems, Inc. vellenga@cadence.com
>270 Billerica Rd
>Chelmsford, MA 01824-4179
>"We all work with partial information."
>----------------------------------------------------------
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>
>] -----Original Message-----
>] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On
>] Behalf Of Michael Rohleder
>] Sent: Wednesday, December 01, 2004 2:03 PM
>] To: SystemVerilog CC DWG
>] Subject: [sv-cc] Errata #63, #158, #330 amended as discussed
>] in today's meeting
>]
>]
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NOTE: The content of this message may contain personal views 
      which are not neccessarily the views of Freescale, unless specifically stated.
 
         ___________________________________________________
        |                                                   |
      _ | Michael Rohleder            Tel: +49-89-92103-259 | _
     / )| Freescale Semiconductor     Fax: +49-89-92103-680 |( \
    / / |      Freescale Halbleiter Deutschland GmbH        | \ \
  _( (_ |  _   Schatzbogen 7, D-81829 Munich, Germany    _  | _) )_
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