[sv-cc] SV-CC agenda for 01/05/2005

Hi All,

The call-in information for this meeting is as follows:

   U.S. 866-807-0627
   International 203-955-5179
   Passcode 399143

Meeting will start at 11:30am EST (4:30pm GMT), and last for 1.5 hours.

   -Chas

AGENDA

1. Review Patent information

  Go to:
    http://standards.ieee.org/board/pat/pat-slideset.ppt

2. Review minutes from last meeting (12/22/2004)
   Ralph reported he was there for the 12/16 meeting, but not the 12/22 meeting.

3. Liaisons

   - Anyone care to make a report?

4. New business

   - Handling PTF items in the two databases.
   - Items 265, 274, 297, and 321
   - Item 52
   - Others?

5. Review SV-CC items with proposals:

6. Review SV-CC items with proposals (Straw poll only):

7. Review old business:

   SV-CC action items:
   - Francoise to ask Peter Ashenden what was done to improve
     printing from Rational Rose.
   - Francoise to inquire about the feasibility of third parties
     shipping the UML for the diagrams.
   - Sachi to drive finding a better solution for 052.
   - JimV to enter a new SV-CC item for adding tables for return values of
     the properties.
   - Doug to update proposal for Item 050 as decided on 12/22/2004.

   PTF action items:
   - Steve to compare BNF with the access available
     for attributes to see if they match
   - Stu to write proposal for PTF 368.
   - Stu to enter new PTF item for save/restart/reset issue.
   - Chas to write proposal for PTF 296.
   - Francoise to lookup wording for PTF 524 in VHPI.
   - Francoise will open a new PTF issue to look for situations like 25.6.15,
     where multiple methods are used access the same object enclosure
   - Chas to reword proposal for PTF 525.
   - Draft a straw man proposal using a clean slate with no concern for
     existing PLI/VPI on the best way to represent all Verilog and
     SystemVerilog kinds and types. This straw man will then be used as a
     basis for discussing backward compatibility with the existing reg, net,
     variables, functions, and parameter diagrams. It may be decided that
     full backward compatibility is not possible, or is not the best approach
     moving forward.
   - Sachi will file a PTF item for the clarification of what can be done
     at ROsync time and putting values in future times.
   - Francoise to file a PTF item that asks to specify the order that iteration
     occur in, when the order is important.
   - Steve to add ETF item for Annex C to remove the Informative label, but
     still allow the contents to be option

-- 
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com