I fixed the mistakes in the implementation of 303 and 311 and moved them back to
the 'acknowledged' state.
You need to give me a final resolution about issues 040 and 313.
Note about 040 that splitting the section into 4 parts will again cause Stu to
have to redo all the cross-references from 1800 to 1364.
Thanks,
Shalom
Charles Dawson wrote:
> Hi Editors,
>
> I found some very minor issues with the following items:
>
> Item 040: diagram for parameter is missing
> Item 303: PTF 342: Deprecate the PLI 1.0 sections
> Item 311: PTF 329: 27.29: vpi_put_data not used in example
>
> For each of these, I have added a bugnote describing the problem.
>
> The following Item needs further work by the SV-CC committee:
>
> Item 313: PTF 296: Generate stmts will need change made in VPI
>
> I will be putting together a description of the issue and/or a new
> proposal shortly.
>
> -Chas
>
> --
> Charles Dawson
> Senior Engineering Manager
> NC-Verilog Team
> Cadence Design Systems, Inc.
> 270 Billerica Road
> Chelmsford, MA 01824
> (978) 262 - 6273
> chas@cadence.com
-- Shalom Bresticker Shalom.Bresticker @freescale.com Design & Verification Methodology Tel: +972 9 9522268 Freescale Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 5441478 [ ]Freescale Internal Use Only [ ]Freescale Confidential ProprietaryReceived on Sat Jan 22 23:06:58 2005
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