[sv-cc] [Fwd: BOUNCE sv-cc@eda.org: Non-member submission from ["Stuart Sutherland" <stuart@sutherland.com>]]

-------- Original Message --------
Subject: BOUNCE sv-cc@eda.org: Non-member submission from ["Stuart Sutherland" <stuart@sutherland.com>]
Date: Thu, 10 Feb 2005 22:54:22 -0800 (PST)
From: owner-sv-cc@eda.org
To: sv-cc-approval@eda.org

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From: "Stuart Sutherland" <stuart@sutherland.com>
To: "'Charles Dawson'" <chas@cadence.com>
Cc: "'SV-CC'" <sv-cc@server.eda.org>
Subject: RE: Passed 373
Date: Fri, 11 Feb 2005 22:54:24 -0800
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Chas,

I have added 373 to P1800/D4. I do have some questions, however.

The second example added as note 6 in 31.46 does not see correct. It reads:

   Example 2:

      [2:0] var [0:3] = '{3: 3'b1, default: 3'b0};

   The assignment pattern which initializes the array variable var uses
   index and default keys...

First off, the declaration does not look correct. Unless I grossly
misunderstand the new data types syntax, it is not legal to start a
declaration with [2:0]. There needs to be some type of keyword before the
opening square bracket.

Second, the paragraph after the example refers to "var" as if it is a
variable name. "var" is a keyword, and cannot be used as a variable name.

Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stu Sutherland
stuart@sutherland.com

> -----Original Message-----
> From: Charles Dawson [mailto:chas@cadence.com]
> Sent: Thursday, February 10, 2005 6:22 PM
> To: stuart@sutherland.com
> Subject: Passed 373
>
> Hi Stu,
>
> Hope this gets to you in time. The SV-CC passed 373.
>
> -Chas
>
>

-- 
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com