[sv-cc] SV-CC agenda for 02/23/2005

Hi All,

The call-in information for this meeting is as follows:

   U.S.               866-807-0627
   International      203-955-5179
   Passcode           399143

Meeting will start at 12:00am EST (5:00pm GMT), and last for 1.0 hours.

   -Chas


AGENDA

1.  Review Patent information

   Go to:
     http://standards.ieee.org/board/pat/pat-slideset.ppt

2.  Review minutes from last meeting (02/09/2005)

3.  Liaisons

   - Anyone care to make a report?

4.  New business

   - Have we completed our review of all Acknowledged items?
   - Review schedule for balloting feedback.
   - Others?

5.  Review SV-CC items with proposals:

6.  Review SV-CC items with proposals (Straw poll only):

7.  Review old business:

   SV-CC action items:
   - Francoise to ask Peter Ashenden what was done to improve
     printing from Rational Rose.
   - Francoise to inquire about the feasibility of third parties
     shipping the UML for the diagrams.
   - JimV to enter a new SV-CC item for adding tables for return values of
     the properties.
   - Stu to file new SV-CC item that will address bigger issue he pointed
     out in Item 321.
   - Francoise and Chas to investigate what to do for systemVerilog and generates

   PTF action items:
   - Steve to compare BNF with the access available
     for attributes to see if they match
   - Stu to enter new PTF item for save/restart/reset issue.
   - Francoise to lookup wording for PTF 524 in VHPI.
   - Francoise will open a new PTF issue to look for situations like 25.6.15,
     where multiple methods are used access the same object enclosure
   - Chas to reword proposal for PTF 525.
   - Francoise to file a PTF item that asks to specify the order that iteration
     occur in, when the order is important.
   - Steve to add ETF item for Annex C to remove the Informative label, but
     still allow the contents to be optional.
   - Chas to file an Item on the usage of the term "tags" at the beginning of
     clause 27.


-- 
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com