[sv-cc] On TRUE/true and FALSE/false

Earlier in the process, we went through and tried to
represent all the Boolean values returned by vpi_get
as consistently TRUE or FALSE.  But we did miss some.

As for function return values (other than for vpi_get),
I agree with you.  Clause 27 of 1364 tends to use
the lower case versions, generally in parentheses.

Regards,
Jim Vellenga

--------------------------------------------------------- 
James H. Vellenga                            978-262-6381 
Engineering Director                   (FAX) 978-262-6636 
Cadence Design Systems, Inc.         vellenga@cadence.com 
270 Billerica Rd 
Chelmsford, MA 01824-4179 
"We all work with partial information." 
---------------------------------------------------------- 
  
 

] -----Original Message-----
] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
] Behalf Of Michael Rohleder
] Sent: Thursday, April 07, 2005 10:50 AM
] To: SystemVerilog CC DWG
] Subject: [sv-cc] Proposal for #426 uploaded
] 
] Hi all,
] 
] I have uploaded a proposal for Mantis item #426 (actually 
] there are two proposal, a and b).
] 
] The reason for this is my observation that - in contrast to 
] the statement made problem report - I do not see
] a standard scheme for the VPI to signal success or failure:
]  - vpi_flush, and vpi_mcd_flush return zero when successful, 
] and non-zero when failing
]  - vpi_free_object, vpi_get_vlog_info, vpi_put_userdata, 
] vpi_remove_cb return one on sucess, and zero on failure
]  - vpi_control returns true when successful and false when failing
] just to give some examples and not to mention some more 
] special cases like vpi_chk_error().
] 
] However, I think the definition of TRUE and FALSE is not in 
] line with the rest of the VPI specification, which
] uses 1 (true) and 0 (false) rather consistently. However I am 
] not sure it makes sense to change a TRUE/FALSE
] mapping to false/true, just to be as inconsistent as before ...
] <></> 
] 
] Therefore I created two proposals, the first a) keeps the 
] TRUE/FALSE mapping to signal success/failure, while
] the second b) reverts this mapping. Choose whichever you want.
] 
] 
] Regards,
] -Michael
] 
] 
] 
] 
] 
] 
] 
] 
] 
] -- 
] 
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