RE: [sv-cc] Definition of full name in 1364

Charles,

Doesn't 12.5 of 1364-2005 give a pretty good explanation
of a unique "hierarchical path name"?  That should be
a pretty good start, and then we do have specific
exceptions listed for elements of packages -- which of
course 1364 does not cover.

The other problem, of course, is that, now that more
than one class var can point to the same class instance,
the path names are not necessarily unique.  So a general
description of a vpiFullName (or of a hierarchical
path name) should reference our notes about that
as well.

Regards,
Jim

--------------------------------------------------------- 
James H. Vellenga                            978-262-6381 
Engineering Director                   (FAX) 978-262-6636 
Cadence Design Systems, Inc.         vellenga@cadence.com 
270 Billerica Rd 
Chelmsford, MA 01824-4179 
"We all work with partial information." 
---------------------------------------------------------- 
  
 

] -----Original Message-----
] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
] Behalf Of Charlie Dawson
] Sent: Thursday, April 14, 2005 3:40 PM
] To: SV-CC
] Subject: [sv-cc] Definition of full name in 1364
] 
] Hi All,
] 
] At the last meeting I took an action to look for the definition of
] vpiFullName in the 1364 specification. This was in reference to
] Mantis Item 610.
] 
] I could not find one, so perhaps we should try to make a definition.
] I know that I have had a view of what vpiFullName should return for
] quite some time, but I'm not sure how to put it into the spec.
] 
] It goes something like this:
]    - Full hierarchical name starting from the top module.
]    - A string which can then be successfully parsed by
]      vpi_handle_by_name() such that the same object would be
]      returned as that with which we started.
]    - The format would also be the same as what $display("%m") might
]      return.  Not sure if this is necessary.
] 
] Am I missing any important points?
] 
]    -Chas
] 
] 
] -- 
] Charles Dawson
] Senior Engineering Manager
] NC-Verilog Team
] Cadence Design Systems, Inc.
] 270 Billerica Road
] Chelmsford, MA  01824
] (978) 262 - 6273
] chas@cadence.com
] 
] 
] 
]