RE: [sv-cc] errata 458

Francoise,

As you noted, the range iteration is actually correct.
But there are two mistakes in the vpiLeftRange and
vpiRightRange relations.  Both of them should be
coming off of logic net only (and not off of time
net).  The original proposal (before the first ballot)
had it correctly, but it got lost in the editing.

Also, (and the original proposal had this wrong),
the vpiLeftRange should only have one arrow.

Regards,
Jim V.

--------------------------------------------------------- 
James H. Vellenga                            978-262-6381 
Engineering Director                   (FAX) 978-262-6636 
Cadence Design Systems, Inc.         vellenga@cadence.com 
270 Billerica Rd 
Chelmsford, MA 01824-4179 
"We all work with partial information." 
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] -----Original Message-----
] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
] Behalf Of Francoise Martinolle
] Sent: Tuesday, May 03, 2005 1:08 PM
] To: sv-cc@eda.org
] Subject: [sv-cc] errata 458
] 
] I responded to errata 458 (added a bug note). There is 
] nothing to correct in the diagram 
] (see my explanation).
]  
] Francoise
]        '
]