RE: [sv-cc] Proposals uploaded

From: Jim Vellenga <vellenga_at_.....>
Date: Fri May 06 2005 - 05:20:10 PDT
Doug, the proposals look good.  485 was especially
clear, and answered most of the questions I had.

One question on 485, though:  The current proposal says
that "A thread is a Verilog process."  This differs
slightly from 10.7, which also identifies the parallel
branches of fork-joins as separate threads.  Do we want
to include the fork-join branches as threads as well?

Regards,
Jim V.

--------------------------------------------------------- 
James H. Vellenga                            978-262-6381 
Engineering Director                   (FAX) 978-262-6636 
Cadence Design Systems, Inc.         vellenga@cadence.com 
270 Billerica Rd 
Chelmsford, MA 01824-4179 
"We all work with partial information." 
---------------------------------------------------------- 
  
 

] -----Original Message-----
] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
] Behalf Of Warmke, Doug
] Sent: Friday, May 06, 2005 1:17 AM
] To: sv-cc@eda.org
] Subject: [sv-cc] Proposals uploaded
] 
] Charles, Team,
] 
] I went through all my assigned items and uploaded proposals:
] 
]   http://www.eda.org/svdb/bug_view_page.php?bug_id=0000418
]   http://www.eda.org/svdb/bug_view_page.php?bug_id=0000449
]   http://www.eda.org/svdb/bug_view_page.php?bug_id=0000483
]   http://www.eda.org/svdb/bug_view_page.php?bug_id=0000485
]   http://www.eda.org/svdb/bug_view_page.php?bug_id=0000685
] 
] Item 706 is over my head, Charles.
] 
]   http://www.eda.org/svdb/bug_view_page.php?bug_id=0000685 
] 
] Could you please assign it to someone else?
] 
] Thanks,
] Doug
] 
] 
] 
Received on Fri May 6 05:20:15 2005

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