[sv-cc] [Fwd: BOUNCE sv-cc@eda.org: Non-member submission from [Neil Korpusik <Neil.Korpusik@Sun.COM>]]

From: Charles Dawson <chas_at_.....>
Date: Mon May 09 2005 - 05:51:32 PDT
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Subject: BOUNCE sv-cc@eda.org:    Non-member submission from [Neil Korpusik <Neil.Korpusik@Sun.COM>]
Date: Sat, 7 May 2005 21:38:04 -0700 (PDT)
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Date: Sat, 07 May 2005 21:37:59 -0700
From: Neil Korpusik <Neil.Korpusik@Sun.COM>
Subject: P1364 meeting minutes - 6th May, 2005
To: "Fitzpatrick, Tom" <tom_fitzpatrick@mentorg.com>, etf@boyd.com,
         sv-cc@server.eda.org, sv-champions@server.eda.org, btf@boyd.com
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The minutes are attached.


Note to SV-Champions: The P1800 BNF and keyword list need to be updated
    to match the 1364 mantis item 680 changes. For the 'begin_keywords
    directive, the appropriate keyword lists must also be updated.


-- 
---------------------------------------------------------------------
Neil Korpusik                                     Tel: 408-720-4852
Staff Engineer                                    Fax: 408-720-4850
Frontend Technologies - ASICs & Processors (FTAP)
Sun Microsystems
email: neil.korpusik@sun.com
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Minutes of P1364-2005 teleconference
6-May-2005

Attendees:
	Tom Fitzpatrick
	Neil Korpusik
	Cliff Cummings
	Steve Sharp
	Brad Pierce
	Mark Hartoog
	Karen Pieper


1. 680 - config

    Cliff  - Verilog configs are easier to use than VHDL configurations.
    Brad   - semicolons - do they need to always be specified?
    Steve  - The semicolons assist with error checking.
	  - In BNF - what are the starting symbols. For Verilog and library
	    map files. We are specifying two languages with one BNF.
	    Steve's config proposal had 'source_text' and 'library_text' as
	    starting symbols. This was a cut and paste error with the A.1.1
             BNF.
    Cliff  - there was agreement to have one list of keywords for both languages.
*  Brad   - A1.1 - file_path_spec                        // delete this
		 - <file_path_spec> --> file_path_spec   // last statement
*  Tom    - A1.3 - source_text ---> verilog_source_text
	    A1.3 --> A1.2
	    A1.4 --> A1.3
	    A1.5 --> A1.4
	    A1.2 --> A1.5
    Brad   - A1.1 - { library_descriptions } --> { library_description }
	    library_descriptions            -->   library_description
    Tom    - suggested a reordering of some BNF
*  Tom    - First new paragraph in 13.1 - should be a note.
*  Steve  - 13.2.1.1 - page 9 - IF ---> If
*  Brad   - 13.2.1.1 - page 8 - file: was confusing
	    (Tom) The example in 13.2.1.1 ("File path resolution") shall be
             changed to a table to illustrate the directory/file structure and
             the contents of each file.
	  - 13.2.1.1 - last para, first sentence - LAST --> last
    Steve  - 13.1.1   - the new sentence - library map files are separate files.
*         - library files --> library map files
	    In the proposed sentence in the 2nd
	    paragraph of 13.1.1 ("A library is not...) should be moved to
	    13.2.1 (to become the 2nd paragraph) and changed to "A library map
	    file is not a Verilog source file description, but is a separate
	    file to describe how design elements from specific source files are
	    bound to symbolic libraries."
	  - lib.map is an example of a library map file name.
    Steve  - design elements appear in libraries
*  Cliff  - 13.2.2 delete statement about comment
    Steve  - 13.2.1 doesn't like solution for /*
           - prefers to allow optional "" around file names
	  - this will eliminate the need for so many examples
*         - Allow optional double-quotes (") to distinguish
	    between a file path ./*.v and the beginning of a comment. Since
	    "file_path_spec" is not explicitly defined in the BNF, no BNF
	    change has to be made for this particular issue.
     Brad  - it is tough to define file_path_spec due to different file systems
             and operating systems.

AI/Cliff  - We need to merge this with P1800 as well.

	  - Steve - BNF and keyword lists for `begin_keywords
		    and keyword list in annex are the only places
     Tom   - we need to approve by 9am on Monday.

     Steve - 13.2.4 concern about compiler directives in the library map
	    files (Cliff added this).  Is it confined to the lib map file or
	    does it survive beyond the end of the file? `ifdef, etc.
      Brad - keep the directives to only apply to library files.
      Tom  - can we have multiple library map files? [Steve - not clear]
	    If there are, then do the compiler directives apply to all of them?
*           Compiler directives get reset when reading Verilog source files.
	    Conditional compilation must terminate before the end of the file.
     Steve - Spill-over if there are multiple library map files - one
	    input stream
	  - Was planning to issue a warning if conditional compilation was
	    not explicitly ended within a file.
      Mark - what can be in a library map file:
	    Not clear why we need this macro capability.
	    Not that useful if don't allow configs in the library map file.
     Steve - Due to the limited use of these directives should we just get
	    rid of the whole thing? Was it part of the ballot issue?
	    Concerned that there may be other issues as well.
     Cliff - Adam wanted to include different library map file contents based
	    on the directives.

*  13.2.4 - get rid of it.  Also references to it in 13.2.2, 13.2.1

     Steve - 13.3.1 - page 10, drop second sentence in here
	  - config binds instances to the logical things
     Tom   - get rid of the first 3 sentences from this paragraph
      Mark - lib map file
	    config - binds instances to cells of logical libraries
     Cliff - the original intent of configs was to eliminate the need for
	    the -v and -y command line options.
     Steve - library map file isn't used to specify where to track down source
	    files. The use model that Cliff is proposing is not the way that
	    the constructs work. Cliff is viewing it flipped around from the
	    way that the tool people are viewing it.
      Tom  - If you have precompiled everything into libraries:
	    lib map file - where to put everything.
	    configurations - are used to specify where to pull from (ie from
	    existing libraries).

* 13.3.1  - remove these two paragraphs.

AI/Cliff  - send the source file and .pdf to Steve. He will take it over.
AI/Steve  - send out an updated proposal by the end of today.
AI/Brad   - open corresponding Mantis item to update the 1800 Annex A &
	    B to remain consistent.

     Cliff - Configs don't do what he thought they did.
     Steve - configs are in terms of cells and libraries, not -y and -v.
	  - had only read up to page 10 of the proposal for this meeting.
	  - he may make a lot of simplifications.

2. Mantis 658 - Cliff notes

    Email vote - 4 yes and 1 no (Cliff - voted not but now yes)

3. Mantis 687 - keyword proposal - part of email vote.

    Email vote - 3 yes and 1 no (Cliff)
    Stu agreed to make some updates based on feedback from Cliff.
    Cliff voted no pending release of an updated proposal from Stu.

4. Mantis 688,705 - boyd 659 - $skew, $timeskew, $fullskew

    We now have a comprehensive proposal from Shalom and Yonghao.
    Approved by acclamation (motion by Fitz).

5. Mantis 669 - Introduction (list of names)

AI/Fitz - ask Mac for his recommendation on Vice Chair for 2005.
           Also ask Stefen to confirm his dates of service.
           No on else needs to be included.

    Straw poll: All in favor.

6. Email vote - mantis 680

    Please vote by Monday morning.



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-- 
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com
Received on Mon May 9 05:51:50 2005

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