RE: [sv-cc] Latest set of Mantis Items with Proposals

 
Add proposal for 719 and bugnote for 717 to the agenda.

-----Original Message-----
From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of Charles
Dawson
Sent: Monday, May 09, 2005 11:20 PM
To: SV-CC
Cc: Johny Srouji
Subject: [sv-cc] Latest set of Mantis Items with Proposals 

Hi All,

I have created an up to date list of Items that have proposals.  This list
is based on input I have received so far.  If you provide a new proposal for
an Item which is not on this list, we will address it at the end of
tomorrow's meeting.

   - Item 257 No vpi access defined for enhanced for loops
   - Item 294 32.22 Waiting process as task or function handle
   - Item 345 VPI changes to support Encryption
   - Item 369 SystemVerilog VPI sections do not deal with generates
   - Item 418 PTF 562 Need to have a vpiTimeConst in the vpi_user.h file
   - Item 426 29.3.2.1 Return value of vpi_get_assertion_info() is backwards
   - Item 445 Several Superseded sections missing information
   - Item 447 32.5 missing types for properties
   - Item 449 32.11 vpiPortType is missing from the include file
   - Item 454 32.11 incorrect format for the 2nd note
   - Item 458 32.13 Question on the range relation
   - Item 463 32.16 should not perpetuate unused functionality
   - Item 472 32.22 Note 1 needs clarification
   - Item 481 32.26 Note 1 needs clarification
   - Item 483 32.28 Should document backwards compatibility issue
   - Item 484 32.28 and 32.29 Should not define callbacks in notes
   - Item 485 32.29 Clarify difference between a thread and a frame
   - Item 526 VPI references to dynamic objects prevent garbage collection
   - Item 606 32.30 Problems with data model for clocking blocks
   - Item 684 32.39 vpiMultiConcat should be vpiMultiConcatOp
   - Item 685 26.6.26 vpiMultiConcat should be vpiMultiConcatOp
   - Item 686 32.34 & 32.36 Which operators for assertion "and" and "or" in
VPI?
   - Item 706 assignment pattern allowed as lvalues
   - Item 717 assignment patterns can be lvalue according to 623
   - Item 718 asymetric casex statement
   - Item 721 Add PLI support for structure and type initialization
   - Item 726 Add vpiAssertion object type into sv_vpi_user.h

FYI, should we resolve all of these Items tomorrow, we will only have
14 Items left in the Assigned state, plus another 35 in the New state, which
includes 26 Items from section 31.

   -Chas

--
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com