RE: [sv-cc] Problems found in sv_vpi_user.h file

Hi,

Is vpiLhs/vpiRhs query supported on vpiContAssignBit object ? According to LRM,
it is supported ( I mean the arrows are from the dotted container box). But 
In Verlilog PLI hand book (Stu's book), the lines are from ContAssign solid 
box and I think that makes more sense. 

I am facing a scenario where the ContAssign is : 
assign { carry_out, sum_out} = ina + inb + carry_in;

Here I do not know how we can create a bit select object of the RHS expression.
 
Another case might be a function call like :  assign a = func(b); 

Can someone please help me with this ? 

- Regards,
Tapati 


 
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>From: "Stuart Sutherland" <stuart@sutherland-hdl.com>
>To: <chas@cadence.com>, "'SV-CC'" <sv-cc@eda.org>
>Subject: RE: [sv-cc] Problems found in sv_vpi_user.h file
>Date: Fri, 3 Jun 2005 11:17:48 -0700
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>Chas,
>
>I suggest you pick one of the Mantis items that affected Annex I, preferably
>one that affected at least some these constants, and adding a bug note to
>correct all of these problems, including the problem Tapati.  They are all
>related to making the header file work, so it seems reasonable to me to add
>these corrections to an item that was also fixing the header file.  The bug
>note should state that it supersedes any values that were assigned to those
>constants by other changes prior to the bug note date.  Amending an
>existing, already approved Mantis item and treating the value changes as
>typographical errors would be much easier than opening a new Mantis item
>going through the approval process at this late date.
>
>Stu
>~~~~~~~~~~~~~~~~~~~~~~~~~
>Stuart Sutherland
>stuart@sutherland-hdl.com
>+1-503-692-0898
>  
>
>> -----Original Message-----
>> From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
>> Behalf Of Charles Dawson
>> Sent: Thursday, June 02, 2005 2:51 PM
>> To: SV-CC
>> Subject: [sv-cc] Problems found in sv_vpi_user.h file
>> 
>> Hi All,
>> 
>> A review of the sv_vpi_user.h file here at Cadence has found the
>> following issues:
>> 
>> 1.  vpiLogicVar is defined as vpiRegVar; should be vpiReg.
>> 
>>    #define vpiLogicVar vpiRegVar
>> 
>> should be
>> 
>>    #define vpiLogicVar vpiReg
>> 
>> 2. vpiClockingBlock == vpiAssert
>>     vpiClockingIODecl == vpiAssume
>>     vpiClassDefn == vpiCover
>>     vpiConstraint == vpiDisableCondition
>>     vpiConstraintOrdering == vpiClockingEvent
>> 
>> These object type defines overlap.  We need
>> to pick different numbers for one or the other
>> of them.
>> 
>> I think it is essential that we resolve these two problems
>> along with the one that Tapati found for the vpiAlwaysType
>> issue.
>> 
>> Stu, please let me know how you would like to handle these
>> things.
>> 
>>    -Chas
>> 
>> -- 
>> Charles Dawson
>> Senior Engineering Manager
>> NC-Verilog Team
>> Cadence Design Systems, Inc.
>> 270 Billerica Road
>> Chelmsford, MA  01824
>> (978) 262 - 6273
>> chas@cadence.com
>> 
>> 
>> 
>> 
>

Tapati Basu