CFP from FDL 05. -- Swapnajit Mittra Project VeriPage ::: http://www.project-veripage.com/ ------------------------------------------------------------------------ Forum on specification and Design Languages - FDL'05 **** CALL FOR PARTICIPATION **** September 27-30, 2005 EPFL, Lausanne, Switzerland GENERAL CHAIR Alain Vachoux, alain.vachoux@epfl.ch An ECSI event co-sponsored by the Swiss Federal Institute of Technology (EPFL) co-sponsored with no financial implication by: Accellera, Ansoft, Cadence, GI, GMM, IEE, IFIP 10.5, ITG, LIFL, Mentor Graphics, Microswiss Network, Synopsys, TU Eindhoven, VDE, VSIA **** Registration discounts available until Sept. 2nd, 2005 **** Full information at <http://www.ecsi.org/fdl> ------------------------------------------------------------------------ The Forum on specification and Design Languages committee is pleased to announce the date and venue for FDL'05. Not a Conference, nor an Exhibition, this is a Workshop for people using design languages and interested in their evolution. It is a venue where advanced researchers can mix with design engineers, to better understand each others perspectives. But also to meet with peers to learn about current advances and deployment techniques. There are three thematic areas over the four days, brought together around a series of Presentation lead workshops, namely: - AMS - Analog, Mixed-Signal and Heterogeneous System Design - CSD - C/C++-Based System Design - UML - UML-Based System Specification & Design. In addition, an EDA vendor track and a PSL session will focus on system -level verification. Finally, several plenary and panel sessions, along with numerous fringe meetings, almost all open, will allow you to sample the current issues vexing the community. FDL is a personal event, it inevitably provides some answers, raises more questions, and frequently enlightens you about aspects of modelling that you had never thought of. With opportunities at lunch, coffee and the social event itself, you will increase your range of valuable contacts in this area so important to your future. FDL'05 Planning *************** Tuesday 27 ---------- Keynote + Plenary Session : European Technology Platforms ENIAC & ARTEMIS Technology Platforms Technology Platforms: How to Deal with Overlap and Create Synergy (R. Zimmermann, European Commission) Plenary Session : Trends and Challenges in Avionics Electronics, (P. Pampagnin, Airbus France) AMS 1 : New Languages - Application of SystemC/SystemC-AMS for the Specification of a Complex Wired Telecommunication System - SystemC-WMS : A Wave Mixed-Signal Simulator - System Model of an inertial navigation system using SystemC-AMS - AMS Extensions for Timed/Untimed System-Level Design Language CSD Tutorial - The SystemC TLM Standard in a Mix-Language World (J. Aynsley, Doulos) GEN : System Model of Control Computation and Communication - An Application of Generalized Supervisor Synthesis to the Control of a Call Center - Modelling Heterogeneous Embedded Systems in DFCharts - Refinement of a Perfectly Synchronous Communication Model onto Nostrum NoC Best-Effort Communication Service Fringe Meetings Wednesday 28 ------------ AMS 2 : Keynote & Design and IP - UML/XML based approach to hierarchical AMS synthesis - Development of VHDL-AMS Libraries for Automative Applications - Top-down hierachical design flow application for an analogue-ISPD-PLL de-modulator design CSD Keynote & OCP TLM - Overcoming issues to reach full adoption and benefit of C/C++based system design methodologies in real System-on-Chip projects, (A. Clouard, ST Microelectronics) - OCP TLM for Architectural Modelling, (T. Kogel, CoWare) Eda Vendor Track-System Verilog in Action / Part 1; (M. Willems, Synopsys; T. Bruckner, Mentor Graphics) AMS 3 : Tolerances and Uncertainties - Semi-Symbolic Simulation of Nonlinear Systems - Tolerance Models in hardware Description Languages - Jitter Tolerance Analysis of Clock and Data Recovery Circuits using Matlab and VHDL-AMS - Linearly graded behavioural analogue performance models using support vector machines and VHDL-AMS CSD 1 : TLM Modelling - Devices modelling in SystemC based on behaviour separation - Building heterogeneous platform simulators in C++ for fun and profit - Implementation of a SystemC based Environment for SoC Verification and Validation - Executable Specification of Novel Display Controllers - Mapping Interface Method Calls over OCP Buses - SOAP Based Distributed Simulation Environment for System-on-Chip (SoC) Design Eda Vendor Track-System Verilog in Action / Part 2 (M. Willems, Synopsys; T. Bruckner, Mentor Graphics) AMS 4 : System Verification and Design Flow - Automatic Generation of a Verification Platform for Heterogeneous Systems Designs - Toward seamless top-down of A/MS systems : an example of systems to block-level design in automative applications - Incorporating SystemC in Analog/Mixed-Signal Design Flow - VHDL/VHDL-AMS Modelling and Simulation of a CMOS Imager IP - VHDL-AMS virtual prototyping in power electronics. the Direct Torque Control case Eda Vendor Track C-Based Design - C based Hardware Design for Wireless Applications - Leveraging the efficiency of C-Based Design with Catapult-C UML/Tutorial System Level Design / Part 1 - Performance Modelling for System-Level Design (P. van der Putten, B. Theelen; J. Voeten, TU Eindhoven) AMS 5 : Modelling - VHDL-AMS Modelling and System Verification Flow for Mixed-Signal System-On-Chip - A VHDL-AMS based Time-Domain Skin Depth Model for Edge Coupled Transmission Stripline - Creating Virtual Prototypes of Complex Micro-Electro-Mechanical Transducers Using Reduced-order Modelling Methods and VHDL-AMS UML Tutorial System Level Design / Part 2 - Performance Modelling for System-Level Design (P. van der Putten; B. Theelen; J. Voeten, TU Eindhoven) Thursday 29 ----------- Plenary Session : Performance Modelling for System-Level-Design AMS Tutorial 1 / Part 1 - Symbolic Circuit Analysis and Automated Behavioural Modelling (R. Sommer, T. Halfmann, J. Broz, Infineon) CSD 2 : Heteregenous Models of Computation - Modelling Environment for Heterogeneous Systems based on Generic MoCs - Processor Centric Specification and Modelling of MPSoCs using ArchC - Mixing Synchronous Reactive and Untimed Models of Computation in SystemC UML 1 : Workflow for embedded System Design - ipPROCESS : a Development Process for Soft IP-Core with Prototyping in FPGA - Meta Modelling of Embedded Systems using Active Databases - Using feature models to automate model transformations - An HW/SW co-design Environment based on UML and SystemC AMS Tutorial 1 / Part 2 - Symbolic Circuit Analysis and Automated Behavioural Modelling (R. Sommer, T. Halfmann, J. Broz, Infineon) CSD 3 : HW/SW Co-design and Synthesis - Interface-Centric Abstraction Level for Rapid Hardware/Software Integration - SystemC Mantic : A high level Modelling and Codesign Framework For Reconfiguration Real Time Systems - Hardware Synthesis of Parallel Machines from SystemC UML 2 : Model Driven Engineering - Compiled and Synthesized UML, a pratical Approach for Codesign - Property-Preservation Synthesis for Unified Control and Data-Oriented Models - Traceability and Interoperability at Different Levels of Abstraction in Model Transformations AMS Tutorial 2 - Closing the Simulation Gap between AMS Design and Verification (O. Zinke, P. Frey, R. Sanborn, Cadence) CSD 4 : Multilangue Design - Towards Behavioural Hierarchy Extensions for SystemC - Embed Scripting inside SystemC - Efficient and Customisable Integration of Temporal Properties into SystemC - Aspect Orientation in System Level Design (short paper) - Automatic synthesis of the Hardware/Software Interface in Multiprocessor Architectures - SystemCXML : An Extensible SystemC Front end Using XML UML 3 : Verification and Validation - StateC : a Power Modelling and Simulation flow for Communication Protocols - Integrating Model-Checking with UML-based SoC Development - Formal Evaluation of Quality of Service for Data Acquisition Systems Fring Meetings Friday 30 --------- UML Keynote : The Gap between Specification and Synthesis (S. Mellor, Mentor Graphics) AMS Tutorial 3 / Part 1 - VHDL-AMS Modelling with SIMPLORER V7.0 (R. Juchem, D. Deverajan, Ansoft) PSL Session / Part 1 - PSL-based online monitoring of digital systems - Extending PSL toward analog circuits and signals - Combination of Assertion and HSAT Methods for automated Test Vector Generation UML 4a : Ongoing Standardization - The UML for SoC profile - The MARTE profile for Real Time and Embedded systems AMS Tutorial 3 / Part 2 - VHDL-AMS Modelling with SIMPLORER V7.0 (R. Juchem, D. Deverajan, Ansoft) PSL Session / Part 2 - EU-Sponsored Deployment of PSL : the Prosyd Project Overview - IEEE 1850 PSL : Overview and Status - Next steps in PSL standardization and deployment UML 4b : Ongoing Standardization - The SysML profile for embedded system modelling - Architecture description in related standards ------------------------------------------------------------------------------------- FDL SECRETARIAT Anne-Marie Bernier, ECSI EM: anne_marie.bernier@ecsi.org Ph: +33 476 63 49 34 $( ___________________________________________________________________ Get Juno Platinum for as low as $6.95/month! Unlimited Internet Access with 250MB of Email Storage. Visit http://www.juno.com/bestoffer to sign up today!Received on Thu Jun 30 08:20:42 2005
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