Hi All, Given the below message, I propose that we begin meeting again next Wednesday, at the usual time of 12:00pm EDT. Exact details follow. Wednesday 10/26/2005 12:00pm EDT (16:00 GMT) 866-807-0627 ID 399143 Please let me know if you can make it. Thanks. -Chas -------- Original Message -------- Subject: Errata committees for the P1800 and the P1364 Date: Mon, 17 Oct 2005 13:04:37 -0700 From: "Karen Pieper" <Karen.Pieper@synopsys.com> To: "Brad Pierce" <Brad.Pierce@synopsys.com>, "Charles Dawson" <chas>, "Eduard Cerny" <Eduard.Cerny@synopsys.com>, "Faisal Haque" <fhaque@cisco.com>, "Ghassan Khoory" <Ghassan.Khoory@synopsys.com>, "Johny Srouji" <srouji@us.ibm.com>, "Karen Pieper" <Karen.Pieper@synopsys.com>, "Matthew.R.Maidment" <Matthew.R.Maidment@intel.com>, "Mehdi Mohtashemi" <Mehdi.Mohtashemi@synopsys.com>, "Neil Korpusik" <Neil.Korpusik@sun.com>, "Tom Fitzpatrick" <tom_fitzpatrick@mentor.com> Hi, all, In the P1800 meeting last week, we decided to start "errata committees" to allow discussion of the status of the various P1800 and P1364 committees. We enhanced the focus of the SV-BC to include updates to the non-PLI sections of the P1364, including P1364 BTF and Encryption. The PLI sections of the P1364 standard are currently covered by the SV-CC and that will continue. Furthermore, P1364 database will be merged with the SystemVerilog Database. As a result, the following committees are authorized to operate: SV-BC, SV-CC, SV-AC, and SV-EC. We will also continue with the Champions as a way to ensure our changes are consistent across the committees. Please feel free to initiate meetings of your teams, I'd suggest once monthly, to discuss errata. Please avoid enhancements until we get authorization from the P1800 to proceed (probably once the standard and a new PAR are approved). Thanks, K -- Charles Dawson Senior Engineering Manager NC-Verilog Team Cadence Design Systems, Inc. 270 Billerica Road Chelmsford, MA 01824 (978) 262 - 6273 chas@cadence.comReceived on Mon Oct 17 13:58:13 2005
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