[sv-cc] [Fwd: BOUNCE sv-cc@eda.org: Non-member submission from ["Faisal Haque \(fhaque\)" <fhaque@cisco.com>]]

From: Charles Dawson <chas_at_.....>
Date: Tue Jan 31 2006 - 11:00:30 PST
-------- Original Message --------
Subject: BOUNCE sv-cc@eda.org:    Non-member submission from ["Faisal Haque \(fhaque\)" <fhaque@cisco.com>]
Date: Tue, 31 Jan 2006 10:54:26 -0800 (PST)
From: owner-sv-cc@eda.org
To: sv-cc-approval@eda.org

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Subject: RE: [sv-ac] Opinion on merging of P1364 and P1800
Date: Tue, 31 Jan 2006 10:54:14 -0800
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Thread-Topic: [sv-ac] Opinion on merging of P1364 and P1800
Thread-Index: AcYjq9SaKe9/RITWSrSh3de0R9RkyQCKAWEAABd8e+AAGU6SAA==
From: "Faisal Haque \(fhaque\)" <fhaque@cisco.com>
To: "Bresticker, Shalom" <shalom.bresticker@intel.com>,
         "Karen Pieper" <Karen.Pieper@synopsys.com>, <sv-bc@server.eda.org>,
         <sv-ac@server.eda.org>, <sv-ec@server.eda.org>, <sv-cc@server.eda.org>
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Shalom,
Thanks for the response.
  I think we need to merge not only the two LRMs but the two committees
and send a clear message about the SystemVerilog and Verilog being one
language.
The tough question for me is when should it be done and how long will it
take.=20
I definitely think it should be done before we start doing any feature
additions to SystemVerilog. However we do have errata to fix.
I am not sure whether it will be more efficient to fix errata on the
combined LRM or on separate LRMs.
=20
If it is possible to merge the two LRMs and fix the errata at the same
time then I would be in favor of doing the LRM merge now, otherwise it
should be done after the errata have been fixed.=20
=20
-Faisal


________________________________

	From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]=20
	Sent: Monday, January 30, 2006 10:51 PM
	To: Faisal Haque (fhaque); Karen Pieper; sv-bc@eda.org;
sv-ac@eda.org; sv-ec@eda.org; sv-cc@eda.org
	Subject: RE: [sv-ac] Opinion on merging of P1364 and P1800
=09
=09

	Hi, Faisal.

	=20

	Without stating my own position (yet) on whether it should be
done, I think these are the main claims:

	=20

	-         Going forward, Verilog should cease to exist as a
separate entity from SystemVerilog, since it is a subset of
SystemVerilog.

	-         The Verilog LRM contains statements, e.g.,
restrictions, which are no longer true in SystemVerilog.

	-         It is difficult and wasteful to maintain 2 LRMs.

	-         SystemVerilog needs a single document which fully
describes it. Today you have 2 LRMs, whose combination describes SV. But
then you have to throw away from the Verilog LRM the statements which
are no longer true in SV.

	-         Some people have the wrong impression that Verilog and
SV are 2 entirely separate incompatible languages instead of SV being a
superset of Verilog.

	=20

	Regards,

	Shalom

	=20

=09
________________________________


	From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf
Of Faisal Haque (fhaque)
	Sent: Monday, January 30, 2006 11:46 PM
	To: Karen Pieper; sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org;
sv-cc@eda.org
	Subject: RE: [sv-ac] Opinion on merging of P1364 and P1800

	=20

	Karen,

	What is the rationale for merging the two LRMs?

	Can someone explain.

	-Faisal

	=20

		=20

	=09
________________________________


		From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org]
On Behalf Of Karen Pieper
		Sent: Friday, January 27, 2006 5:41 PM
		To: sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org;
sv-cc@eda.org
		Subject: [sv-ac] Opinion on merging of P1364 and P1800

		Hi, all,=20

		In the P1800 meeting last week, the Working Group asked
for each of the SV-* committees to provide an opinion on whether or not
to merge the P1364 and the P1800 LRMs into one LRM.  They are interested
in your opinions on:

		1)  How much time will it take us to merge the relevant
parts of the LRM=20
		2)  When you recommend merging the LRM (now, toward the
end of the current 2 year revision cycle, next LRM, never)...=20
		3)  Any other questions or comments that the committees
recommend the study group consider in their decision to develop the next
PAR.

		Committee chairs, I would appreciate it if you would
develop a response reflective of your committee's opinion and forward it
to me after your next committee meeting, preferably no later than the
15th of February.

		Thank you,=20

		Karen Pieper=20


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<DIV dir=3Dltr align=3Dleft><SPAN class=3D505114918-31012006><FONT =
face=3DArial=20
color=3D#0000ff size=3D2>Shalom,</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D505114918-31012006><FONT =
face=3DArial=20
color=3D#0000ff size=3D2>Thanks for the response.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D505114918-31012006><FONT =
face=3DArial=20
color=3D#0000ff size=3D2>&nbsp;I think we need to merge not only the two =
LRMs but=20
the two committees and send a clear message about the SystemVerilog and =
Verilog=20
being one language.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D505114918-31012006><FONT =
face=3DArial=20
color=3D#0000ff size=3D2>The tough question for me is when should it be =
done and how=20
long will it take.&nbsp;</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D505114918-31012006><FONT =
face=3DArial=20
color=3D#0000ff size=3D2>I definitely think it should be done before we =
start doing=20
any feature additions to&nbsp;SystemVerilog. However we do have errata =
to=20
fix.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D505114918-31012006><FONT =
face=3DArial=20
color=3D#0000ff size=3D2>I am not sure whether it will be more efficient =
to fix=20
errata on the combined LRM or&nbsp;on separate LRMs.</FONT></SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN =
class=3D505114918-31012006></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D505114918-31012006><FONT =
face=3DArial=20
color=3D#0000ff size=3D2>If it is possible to merge the two LRMs and fix =
the errata=20
at the same time then I&nbsp;would&nbsp;be in favor of&nbsp;doing the =
LRM merge=20
now, otherwise it should be done after the errata have been=20
fixed.</FONT></SPAN><SPAN class=3D505114918-31012006>&nbsp;</SPAN></DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D505114918-31012006><FONT =
face=3DArial=20
color=3D#0000ff size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV dir=3Dltr align=3Dleft><SPAN class=3D505114918-31012006><FONT =
face=3DArial=20
color=3D#0000ff size=3D2>-Faisal</FONT></SPAN></DIV><BR>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px =
solid; MARGIN-RIGHT: 0px">
   <DIV class=3DOutlookMessageHeader lang=3Den-us dir=3Dltr align=3Dleft>
   <HR tabIndex=3D-1>
   <FONT face=3DTahoma size=3D2><B>From:</B> Bresticker, Shalom=20
   [mailto:shalom.bresticker@intel.com] <BR><B>Sent:</B> Monday, January =
30, 2006=20
   10:51 PM<BR><B>To:</B> Faisal Haque (fhaque); Karen Pieper; =
sv-bc@eda.org;=20
   sv-ac@eda.org; sv-ec@eda.org; sv-cc@eda.org<BR><B>Subject:</B> RE: =
[sv-ac]=20
   Opinion on merging of P1364 and P1800<BR></FONT><BR></DIV>
   <DIV></DIV>
   <DIV class=3DSection1>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial">Hi,=20
   Faisal.<o:p></o:p></SPAN></FONT></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: =
Arial"><o:p>&nbsp;</o:p></SPAN></FONT></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial">Without =
stating my=20
   own position (yet) on whether it should be done, I think these are the =
main=20
   claims:<o:p></o:p></SPAN></FONT></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: =
Arial"><o:p>&nbsp;</o:p></SPAN></FONT></P>
   <P class=3DMsoNormal=20
   style=3D"MARGIN-LEFT: 0.5in; TEXT-INDENT: -0.25in; mso-list: l0 level1 =
lfo1"><![if !supportLists]><FONT=20
   face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial"><SPAN=20
   style=3D"mso-list: Ignore">-<FONT face=3D"Times New Roman" =
size=3D1><SPAN=20
   style=3D"FONT: 7pt 'Times New =
Roman'">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
   </SPAN></FONT></SPAN></SPAN></FONT><![endif]><SPAN dir=3Dltr><FONT =
face=3DArial=20
   color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial">Going =
forward,=20
   Verilog should cease to exist as a separate entity from SystemVerilog, =
since=20
   it is a subset of SystemVerilog.<o:p></o:p></SPAN></FONT></SPAN></P>
   <P class=3DMsoNormal=20
   style=3D"MARGIN-LEFT: 0.5in; TEXT-INDENT: -0.25in; mso-list: l0 level1 =
lfo1"><![if !supportLists]><FONT=20
   face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial"><SPAN=20
   style=3D"mso-list: Ignore">-<FONT face=3D"Times New Roman" =
size=3D1><SPAN=20
   style=3D"FONT: 7pt 'Times New =
Roman'">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
   </SPAN></FONT></SPAN></SPAN></FONT><![endif]><SPAN dir=3Dltr><FONT =
face=3DArial=20
   color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial">The Verilog =
LRM=20
   contains statements, e.g., restrictions, which are no longer true in=20
   SystemVerilog.<o:p></o:p></SPAN></FONT></SPAN></P>
   <P class=3DMsoNormal=20
   style=3D"MARGIN-LEFT: 0.5in; TEXT-INDENT: -0.25in; mso-list: l0 level1 =
lfo1"><![if !supportLists]><FONT=20
   face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial"><SPAN=20
   style=3D"mso-list: Ignore">-<FONT face=3D"Times New Roman" =
size=3D1><SPAN=20
   style=3D"FONT: 7pt 'Times New =
Roman'">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
   </SPAN></FONT></SPAN></SPAN></FONT><![endif]><SPAN dir=3Dltr><FONT =
face=3DArial=20
   color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial">It is =
difficult and=20
   wasteful to maintain 2 LRMs.<o:p></o:p></SPAN></FONT></SPAN></P>
   <P class=3DMsoNormal=20
   style=3D"MARGIN-LEFT: 0.5in; TEXT-INDENT: -0.25in; mso-list: l0 level1 =
lfo1"><![if !supportLists]><FONT=20
   face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial"><SPAN=20
   style=3D"mso-list: Ignore">-<FONT face=3D"Times New Roman" =
size=3D1><SPAN=20
   style=3D"FONT: 7pt 'Times New =
Roman'">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
   </SPAN></FONT></SPAN></SPAN></FONT><![endif]><SPAN dir=3Dltr><FONT =
face=3DArial=20
   color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: =
Arial">SystemVerilog needs a=20
   single document which fully describes it. Today you have 2 LRMs, whose =

   combination describes SV. But then you have to throw away from the =
Verilog LRM=20
   the statements which are no longer true in=20
   SV.<o:p></o:p></SPAN></FONT></SPAN></P>
   <P class=3DMsoNormal=20
   style=3D"MARGIN-LEFT: 0.5in; TEXT-INDENT: -0.25in; mso-list: l0 level1 =
lfo1"><![if !supportLists]><FONT=20
   face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial"><SPAN=20
   style=3D"mso-list: Ignore">-<FONT face=3D"Times New Roman" =
size=3D1><SPAN=20
   style=3D"FONT: 7pt 'Times New =
Roman'">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
   </SPAN></FONT></SPAN></SPAN></FONT><![endif]><SPAN dir=3Dltr><FONT =
face=3DArial=20
   color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: Arial">Some people =
have the=20
   wrong impression that Verilog and SV are 2 entirely separate =
incompatible=20
   languages instead of SV being a superset of=20
   Verilog.<o:p></o:p></SPAN></FONT></SPAN></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: =
Arial"><o:p>&nbsp;</o:p></SPAN></FONT></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: =
Arial">Regards,<o:p></o:p></SPAN></FONT></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: =
Arial">Shalom<o:p></o:p></SPAN></FONT></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D5><SPAN=20
   style=3D"FONT-SIZE: 16pt; COLOR: blue; FONT-FAMILY: =
Arial"><o:p>&nbsp;</o:p></SPAN></FONT></P>
   <DIV=20
   style=3D"BORDER-RIGHT: medium none; PADDING-RIGHT: 0in; BORDER-TOP: =
medium none; PADDING-LEFT: 4pt; PADDING-BOTTOM: 0in; BORDER-LEFT: blue =
1.5pt solid; PADDING-TOP: 0in; BORDER-BOTTOM: medium none">
   <DIV>
   <DIV class=3DMsoNormal style=3D"TEXT-ALIGN: center" =
align=3Dcenter><FONT=20
   face=3D"Times New Roman" size=3D3><SPAN style=3D"FONT-SIZE: 12pt">
   <HR tabIndex=3D-1 align=3Dcenter width=3D"100%" SIZE=3D2>
   </SPAN></FONT></DIV>
   <P class=3DMsoNormal><B><FONT face=3DTahoma size=3D2><SPAN=20
   style=3D"FONT-WEIGHT: bold; FONT-SIZE: 10pt; FONT-FAMILY: =
Tahoma">From:</SPAN></FONT></B><FONT=20
   face=3DTahoma size=3D2><SPAN style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Tahoma">=20
   owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] <B><SPAN=20
   style=3D"FONT-WEIGHT: bold">On Behalf Of </SPAN></B>Faisal Haque=20
   (fhaque)<BR><B><SPAN style=3D"FONT-WEIGHT: bold">Sent:</SPAN></B> =
Monday,=20
   January 30, 2006 11:46 PM<BR><B><SPAN style=3D"FONT-WEIGHT: =
bold">To:</SPAN></B>=20
   Karen Pieper; sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org;=20
   sv-cc@eda.org<BR><B><SPAN style=3D"FONT-WEIGHT: =
bold">Subject:</SPAN></B> RE:=20
   [sv-ac] Opinion on merging of P1364 and=20
   P1800</SPAN></FONT><o:p></o:p></P></DIV>
   <P class=3DMsoNormal><FONT face=3D"Times New Roman" size=3D3><SPAN=20
   style=3D"FONT-SIZE: 12pt"><o:p>&nbsp;</o:p></SPAN></FONT></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D2><SPAN=20
   style=3D"FONT-SIZE: 10pt; COLOR: blue; FONT-FAMILY: =
Arial">Karen,</SPAN></FONT><o:p></o:p></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D2><SPAN=20
   style=3D"FONT-SIZE: 10pt; COLOR: blue; FONT-FAMILY: Arial">What is the =
rationale=20
   for merging the two LRMs?</SPAN></FONT><o:p></o:p></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D2><SPAN=20
   style=3D"FONT-SIZE: 10pt; COLOR: blue; FONT-FAMILY: Arial">Can someone =

   explain.</SPAN></FONT><o:p></o:p></P>
   <P class=3DMsoNormal><FONT face=3DArial color=3Dblue size=3D2><SPAN=20
   style=3D"FONT-SIZE: 10pt; COLOR: blue; FONT-FAMILY: =
Arial">-Faisal</SPAN></FONT><o:p></o:p></P>
   <P class=3DMsoNormal><FONT face=3D"Times New Roman" size=3D3><SPAN=20
   style=3D"FONT-SIZE: 12pt">&nbsp;<o:p></o:p></SPAN></FONT></P>
   <BLOCKQUOTE=20
   style=3D"BORDER-RIGHT: medium none; PADDING-RIGHT: 0in; BORDER-TOP: =
medium none; PADDING-LEFT: 4pt; PADDING-BOTTOM: 0in; MARGIN: 5pt 0in 5pt =
3.75pt; BORDER-LEFT: blue 1.5pt solid; PADDING-TOP: 0in; BORDER-BOTTOM: =
medium none">
     <P class=3DMsoNormal><FONT face=3D"Times New Roman" size=3D3><SPAN=20
     style=3D"FONT-SIZE: 12pt"><o:p>&nbsp;</o:p></SPAN></FONT></P>
     <DIV class=3DMsoNormal style=3D"TEXT-ALIGN: center" =
align=3Dcenter><FONT=20
     face=3D"Times New Roman" size=3D3><SPAN style=3D"FONT-SIZE: 12pt">
     <HR tabIndex=3D-1 align=3Dcenter width=3D"100%" SIZE=3D2>
     </SPAN></FONT></DIV>
     <P class=3DMsoNormal style=3D"MARGIN-BOTTOM: 12pt"><B><FONT =
face=3DTahoma=20
     size=3D2><SPAN=20
     style=3D"FONT-WEIGHT: bold; FONT-SIZE: 10pt; FONT-FAMILY: =
Tahoma">From:</SPAN></FONT></B><FONT=20
     face=3DTahoma size=3D2><SPAN style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Tahoma">=20
     owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] <B><SPAN=20
     style=3D"FONT-WEIGHT: bold">On Behalf Of </SPAN></B>Karen =
Pieper<BR><B><SPAN=20
     style=3D"FONT-WEIGHT: bold">Sent:</SPAN></B> Friday, January 27, =
2006 5:41=20
     PM<BR><B><SPAN style=3D"FONT-WEIGHT: bold">To:</SPAN></B> =
sv-bc@eda.org;=20
     sv-ac@eda.org; sv-ec@eda.org; sv-cc@eda.org<BR><B><SPAN=20
     style=3D"FONT-WEIGHT: bold">Subject:</SPAN></B> [sv-ac] Opinion on =
merging of=20
     P1364 and P1800</SPAN></FONT><o:p></o:p></P>
     <P><FONT face=3DArial size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial"><!-- Converted from =
text/rtf format -->Hi,=20
     all,</SPAN></FONT> <o:p></o:p></P>
     <P><FONT face=3DArial size=3D2><SPAN=20
     style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">In the P1800 meeting =
last week,=20
     the Working Group asked for each of the SV-* committees to provide =
an=20
     opinion on whether or not to merge the P1364 and the P1800 LRMs into =
one=20
     LRM.&nbsp; They are interested in your opinions=20
     on:</SPAN></FONT><o:p></o:p></P>
     <P><FONT face=3DArial size=3D2><SPAN=20
     style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">1)&nbsp; How much time =
will it=20
     take us to merge the relevant parts of the LRM</SPAN></FONT> =
<BR><FONT=20
     face=3DArial size=3D2><SPAN style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">2)&nbsp;=20
     When you recommend merging the LRM (now, toward the end of the =
current 2=20
     year revision cycle, next LRM, never)...</SPAN></FONT> <BR><FONT =
face=3DArial=20
     size=3D2><SPAN style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">3)&nbsp; Any other=20
     questions or comments that the committees recommend the study group =
consider=20
     in their decision to develop the next =
PAR.</SPAN></FONT><o:p></o:p></P>
     <P><FONT face=3DArial size=3D2><SPAN=20
     style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Committee chairs, I =
would=20
     appreciate it if you would develop a response reflective of your =
committee's=20
     opinion and forward it to me after your next committee meeting, =
preferably=20
     no later than the 15th of February.</SPAN></FONT><o:p></o:p></P>
     <P><FONT face=3DArial size=3D2><SPAN=20
     style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Thank =
you,</SPAN></FONT>=20
     <o:p></o:p></P>
     <P><FONT face=3DArial size=3D2><SPAN=20
     style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Karen =
Pieper</SPAN></FONT>=20
     <o:p></o:p></P></BLOCKQUOTE></DIV></DIV></BLOCKQUOTE></BODY></HTML>

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-- 
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com
Received on Tue Jan 31 11:00:49 2006

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