-------- Original Message -------- Subject: BOUNCE sv-cc@eda.org: Non-member submission from ["Bradford Jonathan" <Jonathan.Bradford@Micronas.com>] Date: Tue, 31 Jan 2006 16:53:59 -0800 (PST) From: owner-sv-cc@eda.org To: sv-cc-approval@eda.org >From owner-sv-cc Tue Jan 31 16:53:45 2006 Received: from virtue.micronas.com (mailf.micronas.com [192.166.137.27]) by server.eda.org (8.12.10/8.12.0.Beta7) with ESMTP id k110rg6T005173; Tue, 31 Jan 2006 16:53:44 -0800 (PST) Received: from cain.micronas.com [172.17.88.9] by virtue.micronas.com with XWall v3.36c ; Wed, 1 Feb 2006 01:53:30 +0100 X-MimeOLE: Produced By Microsoft Exchange V6.0.6603.0 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C626C9.EA64A2A6" Subject: RE: [sv-bc] Opinion on merging of P1364 and P1800 Date: Wed, 1 Feb 2006 01:53:28 +0100 Message-ID: <AEA1F6D31E97474BB72174D094A8369C01355B9C@EXCHANGE2.Micronas.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Opinion on merging of P1364 and P1800 Thread-Index: AcYjq9SaKe9/RITWSrSh3de0R9RkyQDFpGkg From: "Bradford Jonathan" <Jonathan.Bradford@Micronas.com> To: "Karen Pieper" <Karen.Pieper@synopsys.com>, <sv-bc@server.eda.org>, <sv-ac@server.eda.org>, <sv-ec@server.eda.org>, <sv-cc@server.eda.org> X-Virus-Scanned: ClamAV 0.83/1263/Tue Jan 31 06:48:20 2006 on server.eda.org X-Virus-Status: Clean This is a multi-part message in MIME format. ------_=_NextPart_001_01C626C9.EA64A2A6 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hello Karen from a user point of view a merged LRM containing the content of P1364 and P1800 meaningfully combined is a very important target that should be put in motion as soon as possible. For users SV adoption: o this emphasises that System Verilog subset and Verilog are the same o eases the evolution of Verilog to System Verilog for users, their managers and design tools / flows o avoids complex explanations as to how P1364 & P1800 relate to each other ... For users LRM comprehension: o allows a cohesive definition of how Verilog features influence System Verilog i.e. generate statements, configurations on SV constructs, e.t.c o allows a clean definition of how System Verilog features build on Verilog i.e. data types on wires, bit vector compared to vector of bits concept, e.t.c o allows a unique definition for features common to System Verilog and Verilog i.e. hierarchy, `define e.t.c o avoids the need to refer to two LRMs o avoids exceptions interpreting Verilog LRM when considered as component of System Verilog o avoids conflicts in System Verilog when considering historic Verilog i.e. compilation unit Of course these benefits would also apply to the committee work, later LRM amendments, duplicated issues, avoiding conflicts between two LRMs and reduction of the danger of divergence e.t.c. There is obviously effort involved, but apparently there is a hiatus in activity and people willing to make a start now before the effort becomes too much later. Regards Jonathan Bradford -----Original Message----- From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Karen = Pieper Sent: Saturday, January 28, 2006 2:41 AM To: sv-bc@eda.org; sv-ac@eda.org; sv-ec@eda.org; sv-cc@eda.org Subject: [sv-bc] Opinion on merging of P1364 and P1800 Hi, all,=20 In the P1800 meeting last week, the Working Group asked for each of the = SV-* committees to provide an opinion on whether or not to merge the = P1364 and the P1800 LRMs into one LRM. They are interested in your = opinions on: 1) How much time will it take us to merge the relevant parts of the LRM = 2) When you recommend merging the LRM (now, toward the end of the = current 2 year revision cycle, next LRM, never)...=20 3) Any other questions or comments that the committees recommend the = study group consider in their decision to develop the next PAR. Committee chairs, I would appreciate it if you would develop a response = reflective of your committee's opinion and forward it to me after your = next committee meeting, preferably no later than the 15th of February. Thank you,=20 Karen Pieper=20 ------_=_NextPart_001_01C626C9.EA64A2A6 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; = charset=3Diso-8859-1"> <TITLE>Opinion on merging of P1364 and P1800</TITLE> <META content=3D"MSHTML 6.00.2800.1476" name=3DGENERATOR></HEAD> <BODY> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2>Hello=20 Karen</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2>from a=20 user point of view a merged LRM containing the content of P1364 and = P1800=20 meaningfully combined is a very important target that should be put = in=20 motion as soon as possible.</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2>For=20 users SV adoption:</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> o this emphasises that System Verilog = subset and=20 Verilog are the same</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> o eases the evolution of Verilog to System = Verilog for=20 users, their managers and design tools / flows</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> o avoids complex explanations as to how = P1364 &=20 P1800 relate to each other ...</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2>For=20 users LRM comprehension:</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> o allows a cohesive definition of how = Verilog features=20 influence System Verilog</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> i.e. generate=20 statements, configurations</FONT> <FONT face=3DArial = color=3D#0000ff size=3D2>on=20 SV constructs, e.t.c</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> o allows a clean definition of how = System Verilog=20 features build on Verilog</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> i.e. data = types on=20 wires, bit vector compared to vector of bits concept, = e.t.c</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> o allows a unique definition for features = common to=20 System Verilog and Verilog</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> i.e.=20 hierarchy, `define e.t.c</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> o avoids the need to refer to two = LRMs</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> o avoids exceptions interpreting Verilog LRM when = considered=20 as component of System Verilog</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> o avoids conflicts in System Verilog when = considering=20 historic Verilog</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> i.e. = compilation=20 unit</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2>Of=20 course these benefits would also apply to the committee work, later LRM=20 amendments, duplicated issues, avoiding conflicts between two = LRMs and=20 reduction of the danger of = divergence e.t.c.</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2>There=20 is obviously effort involved, but apparently there is a hiatus in = activity and=20 people willing to make a start now before the effort becomes too much=20 later.</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2>Regards</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2> Jonathan Bradford</FONT></SPAN></DIV> <DIV><SPAN class=3D787405923-31012006><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></SPAN> </DIV> <BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px"> <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT = face=3DTahoma=20 size=3D2>-----Original Message-----<BR><B>From:</B> = owner-sv-bc@eda.org=20 [mailto:owner-sv-bc@eda.org]<B>On Behalf Of </B>Karen = Pieper<BR><B>Sent:</B>=20 Saturday, January 28, 2006 2:41 AM<BR><B>To:</B> sv-bc@eda.org; = sv-ac@eda.org;=20 sv-ec@eda.org; sv-cc@eda.org<BR><B>Subject:</B> [sv-bc] Opinion on = merging of=20 P1364 and P1800<BR><BR></FONT></DIV><!-- Converted from text/rtf = format --> <P><FONT face=3DArial size=3D2>Hi, all,</FONT> </P> <P><FONT face=3DArial size=3D2>In the P1800 meeting last week, the = Working Group=20 asked for each of the SV-* committees to provide an opinion on whether = or not=20 to merge the P1364 and the P1800 LRMs into one LRM. They are = interested=20 in your opinions on:</FONT></P> <P><FONT face=3DArial size=3D2>1) How much time will it take us = to merge the=20 relevant parts of the LRM</FONT> <BR><FONT face=3DArial = size=3D2>2) When you=20 recommend merging the LRM (now, toward the end of the current 2 year = revision=20 cycle, next LRM, never)...</FONT> <BR><FONT face=3DArial = size=3D2>3) Any=20 other questions or comments that the committees recommend the study = group=20 consider in their decision to develop the next PAR.</FONT></P> <P><FONT face=3DArial size=3D2>Committee chairs, I would appreciate it = if you=20 would develop a response reflective of your committee's opinion and = forward it=20 to me after your next committee meeting, preferably no later than the = 15th of=20 February.</FONT></P> <P><FONT face=3DArial size=3D2>Thank you,</FONT> </P> <P><FONT face=3DArial size=3D2>Karen Pieper</FONT> = </P></BLOCKQUOTE></BODY></HTML> ------_=_NextPart_001_01C626C9.EA64A2A6-- -- Charles Dawson Senior Engineering Manager NC-Verilog Team Cadence Design Systems, Inc. 270 Billerica Road Chelmsford, MA 01824 (978) 262 - 6273 chas@cadence.comReceived on Wed Feb 1 06:35:53 2006
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