[sv-cc] [Fwd: BOUNCE sv-cc@eda.org: Non-member submission from ["Geoffrey.Coram" <Geoffrey.Coram@analog.com>]]

From: Charles Dawson <chas_at_.....>
Date: Fri Feb 03 2006 - 10:33:47 PST
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Subject: BOUNCE sv-cc@eda.org:    Non-member submission from ["Geoffrey.Coram" <Geoffrey.Coram@analog.com>]
Date: Fri, 3 Feb 2006 09:46:13 -0800 (PST)
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Date: Fri, 03 Feb 2006 12:45:58 -0500
From: "Geoffrey.Coram" <Geoffrey.Coram@analog.com>
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To: stuart@sutherland-hdl.com
CC: "'Bresticker, Shalom'" <shalom.bresticker@intel.com>, sv-bc@server.eda.org,
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Subject: Re: [sv-bc] Opinion on merging of P1364 and P1800
References: <200602030911699.SM07504@WileECoyote>
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It's a somewhat different situation, but I certainly find it
a nuisance that the Verilog-AMS LRM is a separate document
from the 1364 LRM on which it is based; the AMS LRM includes
many fundamental Verilog items only by reference, which makes
it hard to look things up.

So, I support doing the merge sooner rather than later.

-Geoffrey



Stuart Sutherland wrote:
 >
 > You mention you have colleagues that use the LRMs, but have you asked them
 > whether they would prefer working with a single LRM or having to refer to
 > two different LRMs for the same language?

-- 
Geoffrey J. Coram, Ph.D.    Staff CAD Engineer
Analog Devices, Inc.
804 Woburn St., MS-422,     Tel (781) 937-1924
Wilmington, MA 01887        Fax (781) 937-1014


-- 
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com
Received on Fri Feb 3 10:33:52 2006

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