RE: [sv-cc] Unpacked array argument index correspondance

Andrzej,

I believe you were going to write up the reasons why
you thought that the lower of the left and right
bounds should correspond to C index 0?  If so, it
would be helpful to have that in advance of the
meeting that we consider Doug's proposal.

Thanks,
Jim

--------------------------------------------------------- 
James H. Vellenga                            978-262-6381 
Engineering Director                   (FAX) 978-262-6636 
Cadence Design Systems, Inc.         vellenga@cadence.com 
270 Billerica Rd 
Chelmsford, MA 01824-4179 
"We all work with partial information." 
---------------------------------------------------------- 
  
 

] -----Original Message-----
] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
] Behalf Of Warmke, Doug
] Sent: Thursday, February 16, 2006 9:03 PM
] To: sv-cc@eda.org
] Subject: RE: [sv-cc] Unpacked array argument index correspondance
] 
] SV-CC,
] 
] I created Mantis #1343
]     http://www.eda.org/svdb/bug_view_page.php?bug_id=0001343
] and uploaded a proposal based on my original + Jim's comments.
] 
] Regards,
] Doug 
] 
] > -----Original Message-----
] > From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
] > Behalf Of Warmke, Doug
] > Sent: Wednesday, February 15, 2006 8:14 AM
] > To: Jim Vellenga; sv-cc@eda.org
] > Subject: RE: [sv-cc] Unpacked array argument index correspondance
] > 
] > Jim,
] > 
] > You are correct!
] > I will enter a Mantis item with a proposal based
] > on my original plus your comments here.
] > 
] > Thank you for the comments.
] > 
] > Regards,
] > Doug 
] > 
] > -----Original Message-----
] > From: Jim Vellenga [mailto:vellenga@cadence.com] 
] > Sent: Wednesday, February 15, 2006 7:19 AM
] > To: Warmke, Doug; sv-cc@eda.org
] > Subject: RE: [sv-cc] Unpacked array argument index correspondance
] > 
] > Doug, I think you've highlighted a problem, but shouldn't
] > it be the leftmost element that corresponds to C index 0?
] > The reasons I think so are the following:
] > 
] > -- IEEE Std 1800-2005 "5.2 Packed and unpacked arrays" says
] > "SystemVerilog accepts a single positive number, as an
] > alternative to a range, to specify the size of an
] > unpacked array, like C. In other words, [size] becomes
] > the same as [0:size-1]."  Hence, the default is to have
] > 0 on the left.
] > 
] > -- The last paragraph in "F.6.6 Mapping between
] > SystemVerilog ranges and C ranges" says that "if logic
] > [2:3][1:3][2:0] b [1:10][31:0] is used in SystemVerilog,
] > it needs to be defined in C as if it were declared in
] > SystemVerilog in the following normalized form:  logic
] > [17:0] b [0:9][0:31]."  Here again, the 0th elements appear
] > on the left.
] > 
] > -- My Kernighan & Ritchie, 2d edition, when it draws
] > a diagram of an array, puts the zeroth element on the
] > left.
] > 
] > Whether or not this corresponds to the "natural order"
] > for the elements is in the mind of the orderer; "natural
] > order" is not a term I would have used.  But I think
] > stating that the leftmost element of the unpacked
] > range corresponds to element 0 of the C range will
] > cause the least confusion for us human beings.
] > 
] > Regards,
] > Jim
] > 
] > --------------------------------------------------------- 
] > James H. Vellenga                            978-262-6381 
] > Engineering Director                   (FAX) 978-262-6636 
] > Cadence Design Systems, Inc.         vellenga@cadence.com 
] > 270 Billerica Rd 
] > Chelmsford, MA 01824-4179 
] > "We all work with partial information." 
] > ---------------------------------------------------------- 
] >   
] >  
] > 
] > ] -----Original Message-----
] > ] From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
] > ] Behalf Of Warmke, Doug
] > ] Sent: Friday, February 10, 2006 7:05 PM
] > ] To: sv-cc@eda.org
] > ] Subject: RE: [sv-cc] Unpacked array argument index correspondance
] > ] 
] > ] Follow-up notes:
] > ] 
] > ] I'm still not used to the DPI Annex being renamed to "Annex F".
] > ] Sorry about that!
] > ] 
] > ] Also, the text in question appears in both F.6.3 and F.6.6.
] > ] My proposal would be to modify the text in both places.
] > ] 
] > ] Regards,
] > ] Doug 
] > ] 
] > ] > -----Original Message-----
] > ] > From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On 
] > ] > Behalf Of Warmke, Doug
] > ] > Sent: Friday, February 10, 2006 4:00 PM
] > ] > To: sv-cc@eda.org
] > ] > Subject: [sv-cc] Unpacked array argument index correspondance
] > ] > 
] > ] > Hello SV-CC,
] > ] > 
] > ] > We recently ran into the following in E.6.6:
] > ] > 
] > ] >    c) The natural order of elements for each dimension in the 
] > ] > layout of
] > ] > an unpacked array shall be used,
] > ] >    i.e., elements with lower indices go first. For 
] > ] SystemVerilog range
] > ] > [L:R], the element with System-
] > ] >    Verilog index min(L,R) has the C index 0 and the element with
] > ] > SystemVerilog index max(L,R)
] > ] >    has the C index abs(L-R).
] > ] > 
] > ] > 
] > ] > This is in conflict with how native array index correspondance
] > ] > is performed in assignment-like contexts (such as an actual to
] > ] > formal argument assignment).
] > ] > 
] > ] > From P1800 5.7:
] > ] >    Assigning to a fixed-size unpacked array requires that the 
] > ] > source and
] > ] > the target both be arrays with the same
] > ] >    number of unpacked dimensions, the length of each 
] > ] dimension be the
] > ] > same, and each element be of an
] > ] >    equivalent type. The same requirements shall be in 
] > ] effect if either
] > ] > or both of the arrays are slices. Assignment
] > ] >    is done by assigning each element of the source array to the
] > ] > corresponding element of the target array.
] > ] >    Element correspondence is defined as leftmost to leftmost, 
] > ] > rightmost
] > ] > to rightmost, irrespective of index values.
] > ] >    For example, if array A is declared as int A[7:0] and 
] > array B is
] > ] > declared as int B[1:8], the assignment
] > ] >    A = B; will assign element B[1] to element A[7], and so 
] > ] > on. Assigning
] > ] > fixed-size unpacked arrays of
] > ] >    nonequivalent type to one another shall result in a 
] > ] compiler error.
] > ] > See 6.9.2.
] > ] > 
] > ] > 
] > ] > Here is an example SystemVerilog design along with its output:
] > ] > 
] > ] > module top;
] > ] >     function void foo(input int ia[4]);
] > ] >         for (int i = 0; i < 4; i++)
] > ] >             $write(" ia[%1d] = %1d ", i, ia[i]);
] > ] >         $write("\n");
] > ] >     endfunction
] > ] > 
] > ] >     int ia1[3:0] = '{0, 1, 2, 3};
] > ] >     int ia2[0:3] = '{0, 1, 2, 3};
] > ] > 
] > ] >     initial begin
] > ] >         $display("\nActual args:");
] > ] >         for (int i = 0; i < 4; i++)
] > ] >             $write("ia1[%1d] = %1d ", i, ia1[i]);
] > ] >         $write("\n");
] > ] >         for (int i = 0; i < 4; i++)
] > ] >             $write("ia2[%1d] = %1d ", i, ia2[i]);
] > ] >         $write("\n");
] > ] >         
] > ] >         $display("\nVerilog function calls:");
] > ] >         foo(ia1);
] > ] >         foo(ia2);
] > ] >     end
] > ] >         
] > ] > endmodule
] > ] > 
] > ] > # 
] > ] > # Actual args:
] > ] > # ia1[0] = 3 ia1[1] = 2 ia1[2] = 1 ia1[3] = 0 
] > ] > # ia2[0] = 0 ia2[1] = 1 ia2[2] = 2 ia2[3] = 3 
] > ] > # 
] > ] > # Verilog function calls:
] > ] > #  ia[0] = 0  ia[1] = 1  ia[2] = 2  ia[3] = 3 
] > ] > #  ia[0] = 0  ia[1] = 1  ia[2] = 2  ia[3] = 3 
] > ] > #
] > ] > 
] > ] > This clearly shows the left-to-left and right-to-right
] > ] > index correspondance.
] > ] > 
] > ] > We should do the same thing when passing unpacked array
] > ] > arguments to DPI calls.  After all, one of DPI's foundational
] > ] > tenets is "Do like the native functions do"... :)
] > ] > 
] > ] > My proposal is to change the above text in F.6.6 as follows:
] > ] > 
] > ] >    c) The natural order of elements for each dimension in the 
] > ] > layout of
] > ] > an unpacked array shall be used,
] > ] >    i.e., for SystemVerilog range [L:R], the rightmost element
] > ] > corresponds to C index 0 and the leftmost
] > ] >    index corresponds with C index abs(L-R).
] > ] > 
] > ] > Discussion?
] > ] > I can enter this into Mantis and create a formal proposal if
] > ] > the committee is generally favorable to this proposal.
] > ] > 
] > ] > Regards,
] > ] > Doug
] > ] > 
] > ] > 
] > ] > 
] > ] > 
] > ] > 
] > ] 
] > ] 
] > 
] > 
] 
]