[sv-cc] FW: [sv-ec] 1800 PAR

 

-----Original Message-----
From: owner-sv-ec@eda-stds.org [mailto:owner-sv-ec@eda-stds.org] On
Behalf Of Bresticker, Shalom
Sent: Sunday, August 13, 2006 7:19 AM
To: sv-ec@eda-stds.org
Subject: [sv-ec] 1800 PAR



-----Original Message-----
From: owner-sv-bc@server.eda-stds.org
[mailto:owner-sv-bc@server.eda-stds.org] On Behalf Of Bresticker, Shalom
Sent: Sunday, August 13, 2006 12:20 PM
To: Maidment, Matthew R; sv-bc@server.eda-stds.org
Subject: RE: [sv-bc] Agenda: August 14 SV-BC CC

That quote is from the general "Need for the Project" part of the PAR.

The specific "Scope" item, which is what really defines the project for
the IEEE, reads:

"SystemVerilog 1800 is a Unified Hardware Design, Specification and
Verification language. Verilog 1364-2005 is a design language. Both
standards were approved by the IEEE-SASB in November 2005. This standard
creates new revisions of the Verilog 1364 and SystemVerilog 1800 IEEE
standards, which include Errata fixes and resolutions; enhancements;
Enhanced assertion language; Merge of Verilog LRM and SystemVerilog 1800
LRM into a single LRM; Integration with AMS; and insures
interoperability with other languages such as SystemC and VHDL."

Shalom


> + PAR Update
> 
>   The latest 1800 PAR was recently approved by the IEEE:
> 
>   http://standards.ieee.org/board/nes/projects/1800.pdf
> 
> "The new revision of the standard will include resolutions and 
> clarifications  to Errata and critical enhancements that will enable 
> successful usage of the  hardware design and verification language.  
> Furthermore, and as  SystemVerilog is a superset of Verilog, the new 
> revision will merge with  Verilog 1364-2005 standard to ensure a 
> single reference manual for users and  EDA vendors alike. The new 
> standard will also enable interoperability with  existing languages 
> such as VHDL and SystemC, as well as integration with  Analog Mixed 
> Signal (AMS)."